* Configure realtime timestamp format. * * @param sh * Pointer to mlx5_dev_ctx_shared object. * @param hca_attr * Pointer to DevX HCA capabilities structure. */
| 1593 | * Pointer to DevX HCA capabilities structure. |
| 1594 | */ |
| 1595 | void |
| 1596 | mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, |
| 1597 | struct mlx5_hca_attr *hca_attr) |
| 1598 | { |
| 1599 | uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); |
| 1600 | uint32_t reg[dw_cnt]; |
| 1601 | int ret = ENOTSUP; |
| 1602 | |
| 1603 | if (hca_attr->access_register_user) |
| 1604 | ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, |
| 1605 | MLX5_REGISTER_ID_MTUTC, 0, |
| 1606 | reg, dw_cnt); |
| 1607 | if (!ret) { |
| 1608 | uint32_t ts_mode; |
| 1609 | |
| 1610 | /* MTUTC register is read successfully. */ |
| 1611 | ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); |
| 1612 | if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) |
| 1613 | sh->dev_cap.rt_timestamp = 1; |
| 1614 | } else { |
| 1615 | /* Kernel does not support register reading. */ |
| 1616 | if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) |
| 1617 | sh->dev_cap.rt_timestamp = 1; |
| 1618 | } |
| 1619 | } |
| 1620 | |
| 1621 | static void |
| 1622 | mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh) |
no test coverage detected