* Dump all the created MRs and the global cache entries. * * @param dev * Pointer to Ethernet device. */
| 1382 | * Pointer to Ethernet device. |
| 1383 | */ |
| 1384 | void |
| 1385 | mlx4_mr_dump_dev(struct rte_eth_dev *dev) |
| 1386 | { |
| 1387 | struct mlx4_priv *priv = dev->data->dev_private; |
| 1388 | struct mlx4_mr *mr; |
| 1389 | int mr_n = 0; |
| 1390 | int chunk_n = 0; |
| 1391 | |
| 1392 | rte_rwlock_read_lock(&priv->mr.rwlock); |
| 1393 | /* Iterate all the existing MRs. */ |
| 1394 | LIST_FOREACH(mr, &priv->mr.mr_list, mr) { |
| 1395 | unsigned int n; |
| 1396 | |
| 1397 | DEBUG("port %u MR[%u], LKey = 0x%x, ms_n = %u, ms_bmp_n = %u", |
| 1398 | dev->data->port_id, mr_n++, |
| 1399 | rte_cpu_to_be_32(mr->ibv_mr->lkey), |
| 1400 | mr->ms_n, mr->ms_bmp_n); |
| 1401 | if (mr->ms_n == 0) |
| 1402 | continue; |
| 1403 | for (n = 0; n < mr->ms_bmp_n; ) { |
| 1404 | struct mlx4_mr_cache ret; |
| 1405 | |
| 1406 | memset(&ret, 0, sizeof(ret)); |
| 1407 | n = mr_find_next_chunk(mr, &ret, n); |
| 1408 | if (!ret.end) |
| 1409 | break; |
| 1410 | DEBUG(" chunk[%u], [0x%" PRIxPTR ", 0x%" PRIxPTR ")", |
| 1411 | chunk_n++, ret.start, ret.end); |
| 1412 | } |
| 1413 | } |
| 1414 | DEBUG("port %u dumping global cache", dev->data->port_id); |
| 1415 | mlx4_mr_btree_dump(&priv->mr.cache); |
| 1416 | rte_rwlock_read_unlock(&priv->mr.rwlock); |
| 1417 | } |
| 1418 | #endif |
| 1419 | |
| 1420 | /** |
no test coverage detected