* Poll completion queue for completions. */
| 345 | * Poll completion queue for completions. |
| 346 | */ |
| 347 | uint32_t |
| 348 | gdma_poll_completion_queue(struct mana_gdma_queue *cq, |
| 349 | struct gdma_comp *gdma_comp, uint32_t max_comp) |
| 350 | { |
| 351 | struct gdma_hardware_completion_entry *cqe; |
| 352 | uint32_t new_owner_bits, old_owner_bits; |
| 353 | uint32_t cqe_owner_bits; |
| 354 | uint32_t num_comp = 0; |
| 355 | struct gdma_hardware_completion_entry *buffer = cq->buffer; |
| 356 | |
| 357 | while (num_comp < max_comp) { |
| 358 | cqe = &buffer[cq->head % cq->count]; |
| 359 | new_owner_bits = (cq->head / cq->count) & |
| 360 | COMPLETION_QUEUE_OWNER_MASK; |
| 361 | old_owner_bits = (cq->head / cq->count - 1) & |
| 362 | COMPLETION_QUEUE_OWNER_MASK; |
| 363 | cqe_owner_bits = cqe->owner_bits; |
| 364 | |
| 365 | DP_LOG(DEBUG, "comp cqe bits 0x%x owner bits 0x%x", |
| 366 | cqe_owner_bits, old_owner_bits); |
| 367 | |
| 368 | /* No new entry */ |
| 369 | if (cqe_owner_bits == old_owner_bits) |
| 370 | break; |
| 371 | |
| 372 | if (cqe_owner_bits != new_owner_bits) { |
| 373 | DRV_LOG(ERR, "CQ overflowed, ID %u cqe 0x%x new 0x%x", |
| 374 | cq->id, cqe_owner_bits, new_owner_bits); |
| 375 | break; |
| 376 | } |
| 377 | |
| 378 | gdma_comp[num_comp].cqe_data = cqe->dma_client_data; |
| 379 | num_comp++; |
| 380 | |
| 381 | cq->head++; |
| 382 | |
| 383 | DP_LOG(DEBUG, "comp new 0x%x old 0x%x cqe 0x%x wq %u sq %u head %u", |
| 384 | new_owner_bits, old_owner_bits, cqe_owner_bits, |
| 385 | cqe->wq_num, cqe->is_sq, cq->head); |
| 386 | } |
| 387 | |
| 388 | /* Make sure the CQE owner bits are checked before we access the data |
| 389 | * in CQE |
| 390 | */ |
| 391 | rte_rmb(); |
| 392 | |
| 393 | return num_comp; |
| 394 | } |
no outgoing calls
no test coverage detected