* [VF] Initializes Transmit Unit. */
| 5873 | * [VF] Initializes Transmit Unit. |
| 5874 | */ |
| 5875 | void __rte_cold |
| 5876 | ixgbevf_dev_tx_init(struct rte_eth_dev *dev) |
| 5877 | { |
| 5878 | struct ixgbe_hw *hw; |
| 5879 | struct ixgbe_tx_queue *txq; |
| 5880 | uint64_t bus_addr; |
| 5881 | uint32_t txctrl; |
| 5882 | uint16_t i; |
| 5883 | |
| 5884 | PMD_INIT_FUNC_TRACE(); |
| 5885 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 5886 | |
| 5887 | /* Setup the Base and Length of the Tx Descriptor Rings */ |
| 5888 | for (i = 0; i < dev->data->nb_tx_queues; i++) { |
| 5889 | txq = dev->data->tx_queues[i]; |
| 5890 | bus_addr = txq->tx_ring_phys_addr; |
| 5891 | IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i), |
| 5892 | (uint32_t)(bus_addr & 0x00000000ffffffffULL)); |
| 5893 | IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i), |
| 5894 | (uint32_t)(bus_addr >> 32)); |
| 5895 | IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i), |
| 5896 | txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc)); |
| 5897 | /* Setup the HW Tx Head and TX Tail descriptor pointers */ |
| 5898 | IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0); |
| 5899 | IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0); |
| 5900 | |
| 5901 | /* |
| 5902 | * Disable Tx Head Writeback RO bit, since this hoses |
| 5903 | * bookkeeping if things aren't delivered in order. |
| 5904 | */ |
| 5905 | txctrl = IXGBE_READ_REG(hw, |
| 5906 | IXGBE_VFDCA_TXCTRL(i)); |
| 5907 | txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; |
| 5908 | IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), |
| 5909 | txctrl); |
| 5910 | } |
| 5911 | } |
| 5912 | |
| 5913 | /* |
| 5914 | * [VF] Start Transmit and Receive Units. |