| 362 | } |
| 363 | |
| 364 | static inline void |
| 365 | ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq, |
| 366 | volatile struct ixgbe_adv_tx_context_desc *ctx_txd, |
| 367 | uint64_t ol_flags, union ixgbe_tx_offload tx_offload, |
| 368 | __rte_unused uint64_t *mdata) |
| 369 | { |
| 370 | uint32_t type_tucmd_mlhl; |
| 371 | uint32_t mss_l4len_idx = 0; |
| 372 | uint32_t ctx_idx; |
| 373 | uint32_t vlan_macip_lens; |
| 374 | union ixgbe_tx_offload tx_offload_mask; |
| 375 | uint32_t seqnum_seed = 0; |
| 376 | |
| 377 | ctx_idx = txq->ctx_curr; |
| 378 | tx_offload_mask.data[0] = 0; |
| 379 | tx_offload_mask.data[1] = 0; |
| 380 | type_tucmd_mlhl = 0; |
| 381 | |
| 382 | /* Specify which HW CTX to upload. */ |
| 383 | mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT); |
| 384 | |
| 385 | if (ol_flags & RTE_MBUF_F_TX_VLAN) |
| 386 | tx_offload_mask.vlan_tci |= ~0; |
| 387 | |
| 388 | /* check if TCP segmentation required for this packet */ |
| 389 | if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { |
| 390 | /* implies IP cksum in IPv4 */ |
| 391 | if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) |
| 392 | type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 | |
| 393 | IXGBE_ADVTXD_TUCMD_L4T_TCP | |
| 394 | IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT; |
| 395 | else |
| 396 | type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 | |
| 397 | IXGBE_ADVTXD_TUCMD_L4T_TCP | |
| 398 | IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT; |
| 399 | |
| 400 | tx_offload_mask.l2_len |= ~0; |
| 401 | tx_offload_mask.l3_len |= ~0; |
| 402 | tx_offload_mask.l4_len |= ~0; |
| 403 | tx_offload_mask.tso_segsz |= ~0; |
| 404 | mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT; |
| 405 | mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT; |
| 406 | } else { /* no TSO, check if hardware checksum is needed */ |
| 407 | if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) { |
| 408 | type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4; |
| 409 | tx_offload_mask.l2_len |= ~0; |
| 410 | tx_offload_mask.l3_len |= ~0; |
| 411 | } |
| 412 | |
| 413 | switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) { |
| 414 | case RTE_MBUF_F_TX_UDP_CKSUM: |
| 415 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP | |
| 416 | IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT; |
| 417 | mss_l4len_idx |= sizeof(struct rte_udp_hdr) |
| 418 | << IXGBE_ADVTXD_L4LEN_SHIFT; |
| 419 | tx_offload_mask.l2_len |= ~0; |
| 420 | tx_offload_mask.l3_len |= ~0; |
| 421 | break; |