* ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX * interrupt * * (Taken from FreeBSD tree) * (yes this is all very magic and confusing :) * * @dev port handle * @entry the register array entry * @vector the MSIX vector for this queue * @type RX/TX/MISC */
| 4804 | * @type RX/TX/MISC |
| 4805 | */ |
| 4806 | static void |
| 4807 | ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type) |
| 4808 | { |
| 4809 | struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 4810 | u32 ivar, index; |
| 4811 | |
| 4812 | vector |= IXGBE_IVAR_ALLOC_VAL; |
| 4813 | |
| 4814 | switch (hw->mac.type) { |
| 4815 | |
| 4816 | case ixgbe_mac_82598EB: |
| 4817 | if (type == -1) |
| 4818 | entry = IXGBE_IVAR_OTHER_CAUSES_INDEX; |
| 4819 | else |
| 4820 | entry += (type * 64); |
| 4821 | index = (entry >> 2) & 0x1F; |
| 4822 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); |
| 4823 | ivar &= ~(0xFF << (8 * (entry & 0x3))); |
| 4824 | ivar |= (vector << (8 * (entry & 0x3))); |
| 4825 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); |
| 4826 | break; |
| 4827 | |
| 4828 | case ixgbe_mac_82599EB: |
| 4829 | case ixgbe_mac_X540: |
| 4830 | if (type == -1) { /* MISC IVAR */ |
| 4831 | index = (entry & 1) * 8; |
| 4832 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); |
| 4833 | ivar &= ~(0xFF << index); |
| 4834 | ivar |= (vector << index); |
| 4835 | IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar); |
| 4836 | } else { /* RX/TX IVARS */ |
| 4837 | index = (16 * (entry & 1)) + (8 * type); |
| 4838 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1)); |
| 4839 | ivar &= ~(0xFF << index); |
| 4840 | ivar |= (vector << index); |
| 4841 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar); |
| 4842 | } |
| 4843 | |
| 4844 | break; |
| 4845 | |
| 4846 | default: |
| 4847 | break; |
| 4848 | } |
| 4849 | } |
| 4850 | |
| 4851 | void __rte_cold |
| 4852 | ixgbe_set_rx_function(struct rte_eth_dev *dev) |