* Start Transmit Units for specified queue. */
| 5568 | * Start Transmit Units for specified queue. |
| 5569 | */ |
| 5570 | int __rte_cold |
| 5571 | ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) |
| 5572 | { |
| 5573 | struct ixgbe_hw *hw; |
| 5574 | struct ixgbe_tx_queue *txq; |
| 5575 | uint32_t txdctl; |
| 5576 | int poll_ms; |
| 5577 | |
| 5578 | PMD_INIT_FUNC_TRACE(); |
| 5579 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 5580 | |
| 5581 | txq = dev->data->tx_queues[tx_queue_id]; |
| 5582 | IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); |
| 5583 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); |
| 5584 | txdctl |= IXGBE_TXDCTL_ENABLE; |
| 5585 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); |
| 5586 | |
| 5587 | /* Wait until TX Enable ready */ |
| 5588 | if (hw->mac.type == ixgbe_mac_82599EB) { |
| 5589 | poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS; |
| 5590 | do { |
| 5591 | rte_delay_ms(1); |
| 5592 | txdctl = IXGBE_READ_REG(hw, |
| 5593 | IXGBE_TXDCTL(txq->reg_idx)); |
| 5594 | } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE)); |
| 5595 | if (!poll_ms) |
| 5596 | PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", |
| 5597 | tx_queue_id); |
| 5598 | } |
| 5599 | rte_wmb(); |
| 5600 | IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); |
| 5601 | dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; |
| 5602 | |
| 5603 | return 0; |
| 5604 | } |
| 5605 | |
| 5606 | /* |
| 5607 | * Stop Transmit Units for specified queue. |
no test coverage detected