| 2613 | } |
| 2614 | |
| 2615 | int __rte_cold |
| 2616 | ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, |
| 2617 | uint16_t queue_idx, |
| 2618 | uint16_t nb_desc, |
| 2619 | unsigned int socket_id, |
| 2620 | const struct rte_eth_txconf *tx_conf) |
| 2621 | { |
| 2622 | const struct rte_memzone *tz; |
| 2623 | struct ixgbe_tx_queue *txq; |
| 2624 | struct ixgbe_hw *hw; |
| 2625 | uint16_t tx_rs_thresh, tx_free_thresh; |
| 2626 | uint64_t offloads; |
| 2627 | |
| 2628 | PMD_INIT_FUNC_TRACE(); |
| 2629 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 2630 | |
| 2631 | offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; |
| 2632 | |
| 2633 | /* |
| 2634 | * Validate number of transmit descriptors. |
| 2635 | * It must not exceed hardware maximum, and must be multiple |
| 2636 | * of IXGBE_ALIGN. |
| 2637 | */ |
| 2638 | if (nb_desc % IXGBE_TXD_ALIGN != 0 || |
| 2639 | (nb_desc > IXGBE_MAX_RING_DESC) || |
| 2640 | (nb_desc < IXGBE_MIN_RING_DESC)) { |
| 2641 | return -EINVAL; |
| 2642 | } |
| 2643 | |
| 2644 | /* |
| 2645 | * The following two parameters control the setting of the RS bit on |
| 2646 | * transmit descriptors. |
| 2647 | * TX descriptors will have their RS bit set after txq->tx_rs_thresh |
| 2648 | * descriptors have been used. |
| 2649 | * The TX descriptor ring will be cleaned after txq->tx_free_thresh |
| 2650 | * descriptors are used or if the number of descriptors required |
| 2651 | * to transmit a packet is greater than the number of free TX |
| 2652 | * descriptors. |
| 2653 | * The following constraints must be satisfied: |
| 2654 | * tx_rs_thresh must be greater than 0. |
| 2655 | * tx_rs_thresh must be less than the size of the ring minus 2. |
| 2656 | * tx_rs_thresh must be less than or equal to tx_free_thresh. |
| 2657 | * tx_rs_thresh must be a divisor of the ring size. |
| 2658 | * tx_free_thresh must be greater than 0. |
| 2659 | * tx_free_thresh must be less than the size of the ring minus 3. |
| 2660 | * tx_free_thresh + tx_rs_thresh must not exceed nb_desc. |
| 2661 | * One descriptor in the TX ring is used as a sentinel to avoid a |
| 2662 | * H/W race condition, hence the maximum threshold constraints. |
| 2663 | * When set to zero use default values. |
| 2664 | */ |
| 2665 | tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? |
| 2666 | tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH); |
| 2667 | /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */ |
| 2668 | tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ? |
| 2669 | nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH; |
| 2670 | if (tx_conf->tx_rs_thresh > 0) |
| 2671 | tx_rs_thresh = tx_conf->tx_rs_thresh; |
| 2672 | if (tx_rs_thresh + tx_free_thresh > nb_desc) { |
nothing calls this directly
no test coverage detected