* Start Receive Units for specified queue. */
| 5486 | * Start Receive Units for specified queue. |
| 5487 | */ |
| 5488 | int __rte_cold |
| 5489 | ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) |
| 5490 | { |
| 5491 | struct ixgbe_hw *hw; |
| 5492 | struct ixgbe_rx_queue *rxq; |
| 5493 | uint32_t rxdctl; |
| 5494 | int poll_ms; |
| 5495 | |
| 5496 | PMD_INIT_FUNC_TRACE(); |
| 5497 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 5498 | |
| 5499 | rxq = dev->data->rx_queues[rx_queue_id]; |
| 5500 | |
| 5501 | /* Allocate buffers for descriptor rings */ |
| 5502 | if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) { |
| 5503 | PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d", |
| 5504 | rx_queue_id); |
| 5505 | return -1; |
| 5506 | } |
| 5507 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); |
| 5508 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
| 5509 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl); |
| 5510 | |
| 5511 | /* Wait until RX Enable ready */ |
| 5512 | poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS; |
| 5513 | do { |
| 5514 | rte_delay_ms(1); |
| 5515 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); |
| 5516 | } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE)); |
| 5517 | if (!poll_ms) |
| 5518 | PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id); |
| 5519 | rte_wmb(); |
| 5520 | IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0); |
| 5521 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1); |
| 5522 | dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; |
| 5523 | |
| 5524 | return 0; |
| 5525 | } |
| 5526 | |
| 5527 | /* |
| 5528 | * Stop Receive Units for specified queue. |
no test coverage detected