| 374 | } |
| 375 | |
| 376 | static inline void |
| 377 | ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf) |
| 378 | { |
| 379 | struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 380 | uint32_t reg; |
| 381 | uint32_t reg_offset, vf_shift; |
| 382 | const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ |
| 383 | const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); |
| 384 | uint8_t nb_q_per_pool; |
| 385 | int i; |
| 386 | |
| 387 | vf_shift = vf & VFRE_MASK; |
| 388 | reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; |
| 389 | |
| 390 | /* enable transmit for vf */ |
| 391 | reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); |
| 392 | reg |= (reg | (1 << vf_shift)); |
| 393 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); |
| 394 | |
| 395 | /* enable all queue drop for IOV */ |
| 396 | nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; |
| 397 | for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) { |
| 398 | IXGBE_WRITE_FLUSH(hw); |
| 399 | reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE; |
| 400 | reg |= i << IXGBE_QDE_IDX_SHIFT; |
| 401 | IXGBE_WRITE_REG(hw, IXGBE_QDE, reg); |
| 402 | } |
| 403 | |
| 404 | /* enable receive for vf */ |
| 405 | reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); |
| 406 | reg |= (reg | (1 << vf_shift)); |
| 407 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); |
| 408 | |
| 409 | /* Enable counting of spoofed packets in the SSVPC register */ |
| 410 | reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); |
| 411 | reg |= (1 << vf_shift); |
| 412 | IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); |
| 413 | |
| 414 | ixgbe_vf_reset_event(dev, vf); |
| 415 | } |
| 416 | |
| 417 | static int |
| 418 | ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf) |
no test coverage detected