| 206 | } |
| 207 | |
| 208 | int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev) |
| 209 | { |
| 210 | uint32_t vtctl, fcrth; |
| 211 | uint32_t vfre_slot, vfre_offset; |
| 212 | uint16_t vf_num; |
| 213 | const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ |
| 214 | const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); |
| 215 | struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); |
| 216 | uint32_t gpie, gcr_ext; |
| 217 | uint32_t vlanctrl; |
| 218 | int i; |
| 219 | |
| 220 | vf_num = dev_num_vf(eth_dev); |
| 221 | if (vf_num == 0) |
| 222 | return -1; |
| 223 | |
| 224 | /* enable VMDq and set the default pool for PF */ |
| 225 | vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); |
| 226 | vtctl |= IXGBE_VMD_CTL_VMDQ_EN; |
| 227 | vtctl &= ~IXGBE_VT_CTL_POOL_MASK; |
| 228 | vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx |
| 229 | << IXGBE_VT_CTL_POOL_SHIFT; |
| 230 | vtctl |= IXGBE_VT_CTL_REPLEN; |
| 231 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl); |
| 232 | |
| 233 | vfre_offset = vf_num & VFRE_MASK; |
| 234 | vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0; |
| 235 | |
| 236 | /* Enable pools reserved to PF only */ |
| 237 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset); |
| 238 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1); |
| 239 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset); |
| 240 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1); |
| 241 | |
| 242 | /* PFDMA Tx General Switch Control Enables VMDQ loopback */ |
| 243 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); |
| 244 | |
| 245 | /* clear VMDq map to permanent rar 0 */ |
| 246 | hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); |
| 247 | |
| 248 | /* clear VMDq map to scan rar 127 */ |
| 249 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0); |
| 250 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0); |
| 251 | |
| 252 | /* set VMDq map to default PF pool */ |
| 253 | hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); |
| 254 | |
| 255 | /* |
| 256 | * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode |
| 257 | */ |
| 258 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); |
| 259 | gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK; |
| 260 | |
| 261 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); |
| 262 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; |
| 263 | gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT; |
| 264 | |
| 265 | switch (RTE_ETH_DEV_SRIOV(eth_dev).active) { |
no test coverage detected