| 6255 | } |
| 6256 | |
| 6257 | int |
| 6258 | ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, |
| 6259 | uint16_t queue_idx, uint32_t tx_rate) |
| 6260 | { |
| 6261 | struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 6262 | uint32_t rf_dec, rf_int; |
| 6263 | uint32_t bcnrc_val; |
| 6264 | uint16_t link_speed = dev->data->dev_link.link_speed; |
| 6265 | |
| 6266 | if (queue_idx >= hw->mac.max_tx_queues) |
| 6267 | return -EINVAL; |
| 6268 | |
| 6269 | if (tx_rate != 0) { |
| 6270 | /* Calculate the rate factor values to set */ |
| 6271 | rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; |
| 6272 | rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; |
| 6273 | rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; |
| 6274 | |
| 6275 | bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; |
| 6276 | bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & |
| 6277 | IXGBE_RTTBCNRC_RF_INT_MASK_M); |
| 6278 | bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); |
| 6279 | } else { |
| 6280 | bcnrc_val = 0; |
| 6281 | } |
| 6282 | |
| 6283 | /* |
| 6284 | * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM |
| 6285 | * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise |
| 6286 | * set as 0x4. |
| 6287 | */ |
| 6288 | if (dev->data->mtu + IXGBE_ETH_OVERHEAD >= IXGBE_MAX_JUMBO_FRAME_SIZE) |
| 6289 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_JUMBO_FRAME); |
| 6290 | else |
| 6291 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_DEFAULT); |
| 6292 | |
| 6293 | /* Set RTTBCNRC of queue X */ |
| 6294 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); |
| 6295 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); |
| 6296 | IXGBE_WRITE_FLUSH(hw); |
| 6297 | |
| 6298 | return 0; |
| 6299 | } |
| 6300 | |
| 6301 | static int |
| 6302 | ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, |
no outgoing calls
no test coverage detected