| 5226 | } |
| 5227 | |
| 5228 | static int |
| 5229 | ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, |
| 5230 | struct rte_eth_rss_reta_entry64 *reta_conf, |
| 5231 | uint16_t reta_size) |
| 5232 | { |
| 5233 | uint16_t i, sp_reta_size; |
| 5234 | uint8_t j, mask; |
| 5235 | uint32_t reta; |
| 5236 | uint16_t idx, shift; |
| 5237 | struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 5238 | uint32_t reta_reg; |
| 5239 | |
| 5240 | PMD_INIT_FUNC_TRACE(); |
| 5241 | sp_reta_size = ixgbe_reta_size_get(hw->mac.type); |
| 5242 | if (reta_size != sp_reta_size) { |
| 5243 | PMD_DRV_LOG(ERR, "The size of hash lookup table configured " |
| 5244 | "(%d) doesn't match the number hardware can supported " |
| 5245 | "(%d)", reta_size, sp_reta_size); |
| 5246 | return -EINVAL; |
| 5247 | } |
| 5248 | |
| 5249 | for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { |
| 5250 | idx = i / RTE_ETH_RETA_GROUP_SIZE; |
| 5251 | shift = i % RTE_ETH_RETA_GROUP_SIZE; |
| 5252 | mask = (uint8_t)((reta_conf[idx].mask >> shift) & |
| 5253 | IXGBE_4_BIT_MASK); |
| 5254 | if (!mask) |
| 5255 | continue; |
| 5256 | |
| 5257 | reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); |
| 5258 | reta = IXGBE_READ_REG(hw, reta_reg); |
| 5259 | for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { |
| 5260 | if (mask & (0x1 << j)) |
| 5261 | reta_conf[idx].reta[shift + j] = |
| 5262 | ((reta >> (CHAR_BIT * j)) & |
| 5263 | IXGBE_8_BIT_MASK); |
| 5264 | } |
| 5265 | } |
| 5266 | |
| 5267 | return 0; |
| 5268 | } |
| 5269 | |
| 5270 | static int |
| 5271 | ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, |
nothing calls this directly
no test coverage detected