| 22 | #include "ionic_rxtx.h" |
| 23 | |
| 24 | static __rte_always_inline void |
| 25 | ionic_tx_flush_sg(struct ionic_tx_qcq *txq) |
| 26 | { |
| 27 | struct ionic_cq *cq = &txq->qcq.cq; |
| 28 | struct ionic_queue *q = &txq->qcq.q; |
| 29 | struct rte_mbuf *txm; |
| 30 | struct ionic_txq_comp *cq_desc_base = cq->base; |
| 31 | volatile struct ionic_txq_comp *cq_desc; |
| 32 | void **info; |
| 33 | uint32_t i; |
| 34 | |
| 35 | cq_desc = &cq_desc_base[cq->tail_idx]; |
| 36 | |
| 37 | while (color_match(cq_desc->color, cq->done_color)) { |
| 38 | cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); |
| 39 | if (cq->tail_idx == 0) |
| 40 | cq->done_color = !cq->done_color; |
| 41 | |
| 42 | /* Prefetch 4 x 16B comp at cq->tail_idx + 4 */ |
| 43 | if ((cq->tail_idx & 0x3) == 0) |
| 44 | rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); |
| 45 | |
| 46 | while (q->tail_idx != rte_le_to_cpu_16(cq_desc->comp_index)) { |
| 47 | /* Prefetch 8 mbuf ptrs at q->tail_idx + 2 */ |
| 48 | rte_prefetch0(IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 2))); |
| 49 | |
| 50 | /* Prefetch next mbuf */ |
| 51 | void **next_info = |
| 52 | IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 1)); |
| 53 | if (next_info[0]) |
| 54 | rte_mbuf_prefetch_part2(next_info[0]); |
| 55 | if (next_info[1]) |
| 56 | rte_mbuf_prefetch_part2(next_info[1]); |
| 57 | |
| 58 | info = IONIC_INFO_PTR(q, q->tail_idx); |
| 59 | for (i = 0; i < q->num_segs; i++) { |
| 60 | txm = info[i]; |
| 61 | if (!txm) |
| 62 | break; |
| 63 | |
| 64 | if (txq->flags & IONIC_QCQ_F_FAST_FREE) |
| 65 | rte_mempool_put(txm->pool, txm); |
| 66 | else |
| 67 | rte_pktmbuf_free_seg(txm); |
| 68 | |
| 69 | info[i] = NULL; |
| 70 | } |
| 71 | |
| 72 | q->tail_idx = Q_NEXT_TO_SRVC(q, 1); |
| 73 | } |
| 74 | |
| 75 | cq_desc = &cq_desc_base[cq->tail_idx]; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | static __rte_always_inline int |
| 80 | ionic_tx_sg(struct ionic_tx_qcq *txq, struct rte_mbuf *txm) |
no test coverage detected