Function ionic_lif_rxq_init

dpdk/drivers/net/ionic/ionic_lif.c:1623–1676

}

int
ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)
{
	struct ionic_qcq *qcq = &rxq->qcq;
	struct ionic_queue *q = &qcq->q;
	struct ionic_lif *lif = qcq->lif;
	struct ionic_cq *cq = &qcq->cq;
	struct ionic_admin_ctx ctx = {
		.pending_work = true,
		.cmd.q_init = {
			.opcode = IONIC_CMD_Q_INIT,
			.type = q->type,
			.ver = lif->qtype_info[q->type].version,
			.index = rte_cpu_to_le_32(q->index),
			.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),
			.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
			.ring_size = rte_log2_u32(q->num_descs),
			.ring_base = rte_cpu_to_le_64(q->base_pa),
			.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
			.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
		},
	};
	int err;

	if (rxq->flags & IONIC_QCQ_F_SG)
		ctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);
	if (rxq->flags & IONIC_QCQ_F_CMB)
		ctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);

	IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index);
	IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa);
	IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
		ctx.cmd.q_init.ring_size);
	IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);

	ionic_q_reset(q);
	ionic_cq_reset(cq);

	err = ionic_adminq_post_wait(lif, &ctx);
	if (err)
		return err;

	q->hw_type = ctx.comp.q_init.hw_type;
	q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
	q->db = ionic_db_map(lif, q);

	rxq->flags |= IONIC_QCQ_F_INITED;

	IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
	IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
	IONIC_PRINT(DEBUG, "rxq->db %p", q->db);

	return 0;
}

static int
ionic_station_set(struct ionic_lif *lif)