| 2589 | } |
| 2590 | |
| 2591 | static int |
| 2592 | ice_dev_close(struct rte_eth_dev *dev) |
| 2593 | { |
| 2594 | struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); |
| 2595 | struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 2596 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 2597 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 2598 | struct ice_adapter *ad = |
| 2599 | ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); |
| 2600 | int ret; |
| 2601 | uint32_t val; |
| 2602 | uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned; |
| 2603 | uint32_t pin_idx = ad->devargs.pin_idx; |
| 2604 | |
| 2605 | if (rte_eal_process_type() != RTE_PROC_PRIMARY) |
| 2606 | return 0; |
| 2607 | |
| 2608 | /* Since stop will make link down, then the link event will be |
| 2609 | * triggered, disable the irq firstly. |
| 2610 | */ |
| 2611 | ice_pf_disable_irq0(hw); |
| 2612 | |
| 2613 | /* Unregister callback func from eal lib, use sync version to |
| 2614 | * make sure all active interrupt callbacks is done, then it's |
| 2615 | * safe to free all resources. |
| 2616 | */ |
| 2617 | rte_intr_callback_unregister_sync(intr_handle, |
| 2618 | ice_interrupt_handler, dev); |
| 2619 | |
| 2620 | ret = ice_dev_stop(dev); |
| 2621 | |
| 2622 | if (!ad->is_safe_mode) |
| 2623 | ice_flow_uninit(ad); |
| 2624 | |
| 2625 | /* release all queue resource */ |
| 2626 | ice_free_queues(dev); |
| 2627 | |
| 2628 | ice_res_pool_destroy(&pf->msix_pool); |
| 2629 | ice_release_vsi(pf->main_vsi); |
| 2630 | ice_sched_cleanup_all(hw); |
| 2631 | ice_free_hw_tbls(hw); |
| 2632 | rte_free(hw->port_info); |
| 2633 | hw->port_info = NULL; |
| 2634 | ice_shutdown_all_ctrlq(hw, true); |
| 2635 | rte_free(pf->proto_xtr); |
| 2636 | pf->proto_xtr = NULL; |
| 2637 | |
| 2638 | /* Uninit TM configuration */ |
| 2639 | ice_tm_conf_uninit(dev); |
| 2640 | |
| 2641 | if (ad->devargs.pps_out_ena) { |
| 2642 | ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0); |
| 2643 | ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0); |
| 2644 | ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0); |
| 2645 | ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0); |
| 2646 | |
| 2647 | val = GLGEN_GPIO_CTL_PIN_DIR_M; |
| 2648 | ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val); |
no test coverage detected