Init the TX queue in hardware */
| 2805 | |
| 2806 | /* Init the TX queue in hardware */ |
| 2807 | int |
| 2808 | i40e_tx_queue_init(struct i40e_tx_queue *txq) |
| 2809 | { |
| 2810 | enum i40e_status_code err = I40E_SUCCESS; |
| 2811 | struct i40e_vsi *vsi = txq->vsi; |
| 2812 | struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); |
| 2813 | uint16_t pf_q = txq->reg_idx; |
| 2814 | struct i40e_hmc_obj_txq tx_ctx; |
| 2815 | uint32_t qtx_ctl; |
| 2816 | |
| 2817 | /* clear the context structure first */ |
| 2818 | memset(&tx_ctx, 0, sizeof(tx_ctx)); |
| 2819 | tx_ctx.new_context = 1; |
| 2820 | tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT; |
| 2821 | tx_ctx.qlen = txq->nb_tx_desc; |
| 2822 | |
| 2823 | #ifdef RTE_LIBRTE_IEEE1588 |
| 2824 | tx_ctx.timesync_ena = 1; |
| 2825 | #endif |
| 2826 | tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]); |
| 2827 | if (vsi->type == I40E_VSI_FDIR) |
| 2828 | tx_ctx.fd_ena = TRUE; |
| 2829 | |
| 2830 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); |
| 2831 | if (err != I40E_SUCCESS) { |
| 2832 | PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context"); |
| 2833 | return err; |
| 2834 | } |
| 2835 | |
| 2836 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); |
| 2837 | if (err != I40E_SUCCESS) { |
| 2838 | PMD_DRV_LOG(ERR, "Failure of set lan tx queue context"); |
| 2839 | return err; |
| 2840 | } |
| 2841 | |
| 2842 | /* Now associate this queue with this PCI function */ |
| 2843 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; |
| 2844 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
| 2845 | I40E_QTX_CTL_PF_INDX_MASK); |
| 2846 | I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
| 2847 | I40E_WRITE_FLUSH(hw); |
| 2848 | |
| 2849 | txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); |
| 2850 | |
| 2851 | return err; |
| 2852 | } |
| 2853 | |
| 2854 | int |
| 2855 | i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq) |
no test coverage detected