| 100 | bool add, bool wait_status); |
| 101 | |
| 102 | static int |
| 103 | i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq) |
| 104 | { |
| 105 | struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi); |
| 106 | struct i40e_hmc_obj_rxq rx_ctx; |
| 107 | int err = I40E_SUCCESS; |
| 108 | |
| 109 | memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq)); |
| 110 | /* Init the RX queue in hardware */ |
| 111 | rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT; |
| 112 | rx_ctx.hbuff = 0; |
| 113 | rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT; |
| 114 | rx_ctx.qlen = rxq->nb_rx_desc; |
| 115 | #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC |
| 116 | rx_ctx.dsize = 1; |
| 117 | #endif |
| 118 | rx_ctx.dtype = i40e_header_split_none; |
| 119 | rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE; |
| 120 | rx_ctx.rxmax = I40E_ETH_MAX_LEN; |
| 121 | rx_ctx.tphrdesc_ena = 1; |
| 122 | rx_ctx.tphwdesc_ena = 1; |
| 123 | rx_ctx.tphdata_ena = 1; |
| 124 | rx_ctx.tphhead_ena = 1; |
| 125 | rx_ctx.lrxqthresh = 2; |
| 126 | rx_ctx.crcstrip = 0; |
| 127 | rx_ctx.l2tsel = 1; |
| 128 | rx_ctx.showiv = 0; |
| 129 | rx_ctx.prefena = 1; |
| 130 | |
| 131 | err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx); |
| 132 | if (err != I40E_SUCCESS) { |
| 133 | PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context."); |
| 134 | return err; |
| 135 | } |
| 136 | err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx); |
| 137 | if (err != I40E_SUCCESS) { |
| 138 | PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context."); |
| 139 | return err; |
| 140 | } |
| 141 | rxq->qrx_tail = hw->hw_addr + |
| 142 | I40E_QRX_TAIL(rxq->vsi->base_queue); |
| 143 | |
| 144 | rte_wmb(); |
| 145 | /* Init the RX tail register. */ |
| 146 | I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); |
| 147 | |
| 148 | return err; |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * i40e_fdir_setup - reserve and initialize the Flow Director resources |
no test coverage detected