| 1932 | } |
| 1933 | |
| 1934 | void |
| 1935 | i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi) |
| 1936 | { |
| 1937 | struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi); |
| 1938 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 1939 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 1940 | struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); |
| 1941 | uint16_t msix_vect = vsi->msix_intr; |
| 1942 | uint16_t i; |
| 1943 | |
| 1944 | for (i = 0; i < vsi->nb_qps; i++) { |
| 1945 | I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); |
| 1946 | I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); |
| 1947 | rte_wmb(); |
| 1948 | } |
| 1949 | |
| 1950 | if (vsi->type != I40E_VSI_SRIOV) { |
| 1951 | if (!rte_intr_allow_others(intr_handle)) { |
| 1952 | I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, |
| 1953 | I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); |
| 1954 | I40E_WRITE_REG(hw, |
| 1955 | I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), |
| 1956 | 0); |
| 1957 | } else { |
| 1958 | I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), |
| 1959 | I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); |
| 1960 | I40E_WRITE_REG(hw, |
| 1961 | I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, |
| 1962 | msix_vect - 1), 0); |
| 1963 | } |
| 1964 | } else { |
| 1965 | uint32_t reg; |
| 1966 | reg = (hw->func_caps.num_msix_vectors_vf - 1) * |
| 1967 | vsi->user_param + (msix_vect - 1); |
| 1968 | |
| 1969 | I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), |
| 1970 | I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); |
| 1971 | } |
| 1972 | I40E_WRITE_FLUSH(hw); |
| 1973 | } |
| 1974 | |
| 1975 | static void |
| 1976 | __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect, |
no test coverage detected