| 2127 | } |
| 2128 | |
| 2129 | void |
| 2130 | i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi) |
| 2131 | { |
| 2132 | struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi); |
| 2133 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 2134 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 2135 | struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); |
| 2136 | struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); |
| 2137 | uint16_t msix_intr, i; |
| 2138 | |
| 2139 | if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) |
| 2140 | for (i = 0; i < vsi->nb_msix; i++) { |
| 2141 | msix_intr = vsi->msix_intr + i; |
| 2142 | I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), |
| 2143 | I40E_PFINT_DYN_CTLN_INTENA_MASK | |
| 2144 | I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | |
| 2145 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); |
| 2146 | } |
| 2147 | else |
| 2148 | I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, |
| 2149 | I40E_PFINT_DYN_CTL0_INTENA_MASK | |
| 2150 | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | |
| 2151 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); |
| 2152 | |
| 2153 | I40E_WRITE_FLUSH(hw); |
| 2154 | } |
| 2155 | |
| 2156 | void |
| 2157 | i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi) |
no test coverage detected