| 10408 | } |
| 10409 | |
| 10410 | static int |
| 10411 | i40e_timesync_enable(struct rte_eth_dev *dev) |
| 10412 | { |
| 10413 | struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 10414 | uint32_t tsync_ctl_l; |
| 10415 | uint32_t tsync_ctl_h; |
| 10416 | |
| 10417 | /* Stop the timesync system time. */ |
| 10418 | I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); |
| 10419 | I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); |
| 10420 | /* Reset the timesync system time value. */ |
| 10421 | I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0); |
| 10422 | I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0); |
| 10423 | |
| 10424 | i40e_start_timecounters(dev); |
| 10425 | |
| 10426 | /* Clear timesync registers. */ |
| 10427 | I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); |
| 10428 | I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); |
| 10429 | I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0)); |
| 10430 | I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1)); |
| 10431 | I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2)); |
| 10432 | I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3)); |
| 10433 | |
| 10434 | /* Enable timestamping of PTP packets. */ |
| 10435 | tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); |
| 10436 | tsync_ctl_l |= I40E_PRTTSYN_TSYNENA; |
| 10437 | |
| 10438 | tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); |
| 10439 | tsync_ctl_h |= I40E_PRTTSYN_TSYNENA; |
| 10440 | tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE; |
| 10441 | |
| 10442 | I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); |
| 10443 | I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); |
| 10444 | |
| 10445 | return 0; |
| 10446 | } |
| 10447 | |
| 10448 | static int |
| 10449 | i40e_timesync_disable(struct rte_eth_dev *dev) |
nothing calls this directly
no test coverage detected