* i40e_clear_hw - clear out any left over hw state * @hw: pointer to the hw struct * * Clear queues and interrupts, typically called at init time, * but after the capabilities have been found so we know how many * queues and msix vectors have been allocated. **/
| 1437 | * queues and msix vectors have been allocated. |
| 1438 | **/ |
| 1439 | void i40e_clear_hw(struct i40e_hw *hw) |
| 1440 | { |
| 1441 | u32 num_queues, base_queue; |
| 1442 | u32 num_pf_int; |
| 1443 | u32 num_vf_int; |
| 1444 | u32 num_vfs; |
| 1445 | u32 i, j; |
| 1446 | u32 val; |
| 1447 | u32 eol = 0x7ff; |
| 1448 | |
| 1449 | /* get number of interrupts, queues, and vfs */ |
| 1450 | val = rd32(hw, I40E_GLPCI_CNF2); |
| 1451 | num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> |
| 1452 | I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; |
| 1453 | num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> |
| 1454 | I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; |
| 1455 | |
| 1456 | val = rd32(hw, I40E_PFLAN_QALLOC); |
| 1457 | base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> |
| 1458 | I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; |
| 1459 | j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> |
| 1460 | I40E_PFLAN_QALLOC_LASTQ_SHIFT; |
| 1461 | if (val & I40E_PFLAN_QALLOC_VALID_MASK) |
| 1462 | num_queues = (j - base_queue) + 1; |
| 1463 | else |
| 1464 | num_queues = 0; |
| 1465 | |
| 1466 | val = rd32(hw, I40E_PF_VT_PFALLOC); |
| 1467 | i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> |
| 1468 | I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; |
| 1469 | j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> |
| 1470 | I40E_PF_VT_PFALLOC_LASTVF_SHIFT; |
| 1471 | if (val & I40E_PF_VT_PFALLOC_VALID_MASK) |
| 1472 | num_vfs = (j - i) + 1; |
| 1473 | else |
| 1474 | num_vfs = 0; |
| 1475 | |
| 1476 | /* stop all the interrupts */ |
| 1477 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); |
| 1478 | val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; |
| 1479 | for (i = 0; i < num_pf_int - 2; i++) |
| 1480 | wr32(hw, I40E_PFINT_DYN_CTLN(i), val); |
| 1481 | |
| 1482 | /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ |
| 1483 | val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; |
| 1484 | wr32(hw, I40E_PFINT_LNKLST0, val); |
| 1485 | for (i = 0; i < num_pf_int - 2; i++) |
| 1486 | wr32(hw, I40E_PFINT_LNKLSTN(i), val); |
| 1487 | val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; |
| 1488 | for (i = 0; i < num_vfs; i++) |
| 1489 | wr32(hw, I40E_VPINT_LNKLST0(i), val); |
| 1490 | for (i = 0; i < num_vf_int - 2; i++) |
| 1491 | wr32(hw, I40E_VPINT_LNKLSTN(i), val); |
| 1492 | |
| 1493 | /* warn the HW of the coming Tx disables */ |
| 1494 | for (i = 0; i < num_queues; i++) { |
| 1495 | u32 abs_queue_idx = base_queue + i; |
| 1496 | u32 reg_block = 0; |
no test coverage detected