| 1207 | } |
| 1208 | |
| 1209 | static int enic_check_devargs(struct rte_eth_dev *dev) |
| 1210 | { |
| 1211 | static const char *const valid_keys[] = { |
| 1212 | ENIC_DEVARG_CQ64, |
| 1213 | ENIC_DEVARG_DISABLE_OVERLAY, |
| 1214 | ENIC_DEVARG_ENABLE_AVX2_RX, |
| 1215 | ENIC_DEVARG_IG_VLAN_REWRITE, |
| 1216 | ENIC_DEVARG_REPRESENTOR, |
| 1217 | NULL}; |
| 1218 | struct enic *enic = pmd_priv(dev); |
| 1219 | struct rte_kvargs *kvlist; |
| 1220 | |
| 1221 | ENICPMD_FUNC_TRACE(); |
| 1222 | |
| 1223 | enic->cq64_request = true; /* Use 64B entry if available */ |
| 1224 | enic->disable_overlay = false; |
| 1225 | enic->enable_avx2_rx = false; |
| 1226 | enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; |
| 1227 | if (!dev->device->devargs) |
| 1228 | return 0; |
| 1229 | kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); |
| 1230 | if (!kvlist) |
| 1231 | return -EINVAL; |
| 1232 | if (rte_kvargs_process(kvlist, ENIC_DEVARG_CQ64, |
| 1233 | enic_parse_zero_one, enic) < 0 || |
| 1234 | rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, |
| 1235 | enic_parse_zero_one, enic) < 0 || |
| 1236 | rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, |
| 1237 | enic_parse_zero_one, enic) < 0 || |
| 1238 | rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, |
| 1239 | enic_parse_ig_vlan_rewrite, enic) < 0) { |
| 1240 | rte_kvargs_free(kvlist); |
| 1241 | return -EINVAL; |
| 1242 | } |
| 1243 | rte_kvargs_free(kvlist); |
| 1244 | return 0; |
| 1245 | } |
| 1246 | |
| 1247 | /* Initialize the driver for PF */ |
| 1248 | static int eth_enic_dev_init(struct rte_eth_dev *eth_dev, |
no test coverage detected