| 2817 | } |
| 2818 | |
| 2819 | int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) |
| 2820 | { |
| 2821 | struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; |
| 2822 | struct ena_rss *rss = &ena_dev->rss; |
| 2823 | struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; |
| 2824 | struct ena_admin_set_feat_cmd cmd; |
| 2825 | struct ena_admin_set_feat_resp resp; |
| 2826 | int ret; |
| 2827 | |
| 2828 | if (!ena_com_check_supported_feature_id(ena_dev, |
| 2829 | ENA_ADMIN_RSS_HASH_INPUT)) { |
| 2830 | ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", |
| 2831 | ENA_ADMIN_RSS_HASH_INPUT); |
| 2832 | return ENA_COM_UNSUPPORTED; |
| 2833 | } |
| 2834 | |
| 2835 | memset(&cmd, 0x0, sizeof(cmd)); |
| 2836 | |
| 2837 | cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; |
| 2838 | cmd.aq_common_descriptor.flags = |
| 2839 | ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; |
| 2840 | cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; |
| 2841 | cmd.u.flow_hash_input.enabled_input_sort = |
| 2842 | ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | |
| 2843 | ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; |
| 2844 | |
| 2845 | ret = ena_com_mem_addr_set(ena_dev, |
| 2846 | &cmd.control_buffer.address, |
| 2847 | rss->hash_ctrl_dma_addr); |
| 2848 | if (unlikely(ret)) { |
| 2849 | ena_trc_err(ena_dev, "Memory address set failed\n"); |
| 2850 | return ret; |
| 2851 | } |
| 2852 | cmd.control_buffer.length = sizeof(*hash_ctrl); |
| 2853 | |
| 2854 | ret = ena_com_execute_admin_command(admin_queue, |
| 2855 | (struct ena_admin_aq_entry *)&cmd, |
| 2856 | sizeof(cmd), |
| 2857 | (struct ena_admin_acq_entry *)&resp, |
| 2858 | sizeof(resp)); |
| 2859 | if (unlikely(ret)) |
| 2860 | ena_trc_err(ena_dev, "Failed to set hash input. error: %d\n", ret); |
| 2861 | |
| 2862 | return ret; |
| 2863 | } |
| 2864 | |
| 2865 | int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) |
| 2866 | { |
no test coverage detected