| 946 | } |
| 947 | |
| 948 | static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, |
| 949 | struct ena_com_io_sq *io_sq, |
| 950 | struct ena_com_io_cq *io_cq) |
| 951 | { |
| 952 | size_t size; |
| 953 | |
| 954 | if (io_cq->cdesc_addr.virt_addr) { |
| 955 | size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; |
| 956 | |
| 957 | ENA_MEM_FREE_COHERENT(ena_dev->dmadev, |
| 958 | size, |
| 959 | io_cq->cdesc_addr.virt_addr, |
| 960 | io_cq->cdesc_addr.phys_addr, |
| 961 | io_cq->cdesc_addr.mem_handle); |
| 962 | |
| 963 | io_cq->cdesc_addr.virt_addr = NULL; |
| 964 | } |
| 965 | |
| 966 | if (io_sq->desc_addr.virt_addr) { |
| 967 | size = io_sq->desc_entry_size * io_sq->q_depth; |
| 968 | |
| 969 | ENA_MEM_FREE_COHERENT(ena_dev->dmadev, |
| 970 | size, |
| 971 | io_sq->desc_addr.virt_addr, |
| 972 | io_sq->desc_addr.phys_addr, |
| 973 | io_sq->desc_addr.mem_handle); |
| 974 | |
| 975 | io_sq->desc_addr.virt_addr = NULL; |
| 976 | } |
| 977 | |
| 978 | if (io_sq->bounce_buf_ctrl.base_buffer) { |
| 979 | ENA_MEM_FREE(ena_dev->dmadev, |
| 980 | io_sq->bounce_buf_ctrl.base_buffer, |
| 981 | (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT)); |
| 982 | io_sq->bounce_buf_ctrl.base_buffer = NULL; |
| 983 | } |
| 984 | } |
| 985 | |
| 986 | static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, |
| 987 | u16 exp_state) |
no outgoing calls
no test coverage detected