| 411 | } |
| 412 | |
| 413 | static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, |
| 414 | struct ena_com_create_io_ctx *ctx, |
| 415 | struct ena_com_io_cq *io_cq) |
| 416 | { |
| 417 | size_t size; |
| 418 | int prev_node = 0; |
| 419 | |
| 420 | memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); |
| 421 | |
| 422 | /* Use the basic completion descriptor for Rx */ |
| 423 | io_cq->cdesc_entry_size_in_bytes = |
| 424 | (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? |
| 425 | sizeof(struct ena_eth_io_tx_cdesc) : |
| 426 | sizeof(struct ena_eth_io_rx_cdesc_base); |
| 427 | |
| 428 | size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; |
| 429 | io_cq->bus = ena_dev->bus; |
| 430 | |
| 431 | ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(ena_dev->dmadev, |
| 432 | size, |
| 433 | io_cq->cdesc_addr.virt_addr, |
| 434 | io_cq->cdesc_addr.phys_addr, |
| 435 | io_cq->cdesc_addr.mem_handle, |
| 436 | ctx->numa_node, |
| 437 | prev_node, |
| 438 | ENA_CDESC_RING_SIZE_ALIGNMENT); |
| 439 | if (!io_cq->cdesc_addr.virt_addr) { |
| 440 | ENA_MEM_ALLOC_COHERENT_ALIGNED(ena_dev->dmadev, |
| 441 | size, |
| 442 | io_cq->cdesc_addr.virt_addr, |
| 443 | io_cq->cdesc_addr.phys_addr, |
| 444 | io_cq->cdesc_addr.mem_handle, |
| 445 | ENA_CDESC_RING_SIZE_ALIGNMENT); |
| 446 | } |
| 447 | |
| 448 | if (!io_cq->cdesc_addr.virt_addr) { |
| 449 | ena_trc_err(ena_dev, "Memory allocation failed\n"); |
| 450 | return ENA_COM_NO_MEM; |
| 451 | } |
| 452 | |
| 453 | io_cq->phase = 1; |
| 454 | io_cq->head = 0; |
| 455 | |
| 456 | return 0; |
| 457 | } |
| 458 | |
| 459 | static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, |
| 460 | struct ena_admin_acq_entry *cqe) |
no test coverage detected