| 1606 | } |
| 1607 | |
| 1608 | int ena_com_get_dma_width(struct ena_com_dev *ena_dev) |
| 1609 | { |
| 1610 | u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); |
| 1611 | u32 width; |
| 1612 | |
| 1613 | if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { |
| 1614 | ena_trc_err(ena_dev, "Reg read timeout occurred\n"); |
| 1615 | return ENA_COM_TIMER_EXPIRED; |
| 1616 | } |
| 1617 | |
| 1618 | width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> |
| 1619 | ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; |
| 1620 | |
| 1621 | ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width); |
| 1622 | |
| 1623 | if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { |
| 1624 | ena_trc_err(ena_dev, "DMA width illegal value: %d\n", width); |
| 1625 | return ENA_COM_INVAL; |
| 1626 | } |
| 1627 | |
| 1628 | ena_dev->dma_addr_bits = width; |
| 1629 | |
| 1630 | return width; |
| 1631 | } |
| 1632 | |
| 1633 | int ena_com_validate_version(struct ena_com_dev *ena_dev) |
| 1634 | { |
no test coverage detected