| 2416 | } |
| 2417 | |
| 2418 | int ena_com_dev_reset(struct ena_com_dev *ena_dev, |
| 2419 | enum ena_regs_reset_reason_types reset_reason) |
| 2420 | { |
| 2421 | u32 reset_reason_msb, reset_reason_lsb; |
| 2422 | u32 stat, timeout, cap, reset_val; |
| 2423 | int rc; |
| 2424 | |
| 2425 | stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); |
| 2426 | cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); |
| 2427 | |
| 2428 | if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || |
| 2429 | (cap == ENA_MMIO_READ_TIMEOUT))) { |
| 2430 | ena_trc_err(ena_dev, "Reg read32 timeout occurred\n"); |
| 2431 | return ENA_COM_TIMER_EXPIRED; |
| 2432 | } |
| 2433 | |
| 2434 | if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { |
| 2435 | ena_trc_err(ena_dev, "Device isn't ready, can't reset device\n"); |
| 2436 | return ENA_COM_INVAL; |
| 2437 | } |
| 2438 | |
| 2439 | timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> |
| 2440 | ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; |
| 2441 | if (timeout == 0) { |
| 2442 | ena_trc_err(ena_dev, "Invalid timeout value\n"); |
| 2443 | return ENA_COM_INVAL; |
| 2444 | } |
| 2445 | |
| 2446 | /* start reset */ |
| 2447 | reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; |
| 2448 | |
| 2449 | /* For backward compatibility, device will interpret |
| 2450 | * bits 24-27 as MSB, bits 28-31 as LSB |
| 2451 | */ |
| 2452 | reset_reason_lsb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_LSB_MASK, |
| 2453 | ENA_RESET_REASON_LSB_OFFSET); |
| 2454 | |
| 2455 | reset_reason_msb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_MSB_MASK, |
| 2456 | ENA_RESET_REASON_MSB_OFFSET); |
| 2457 | |
| 2458 | reset_val |= reset_reason_lsb << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT; |
| 2459 | |
| 2460 | if (ena_com_get_cap(ena_dev, ENA_ADMIN_EXTENDED_RESET_REASONS)) { |
| 2461 | reset_val |= reset_reason_msb << ENA_REGS_DEV_CTL_RESET_REASON_EXT_SHIFT; |
| 2462 | } else if (reset_reason_msb) { |
| 2463 | /* In case the device does not support intended |
| 2464 | * extended reset reason fallback to generic |
| 2465 | */ |
| 2466 | reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; |
| 2467 | reset_val |= (ENA_REGS_RESET_GENERIC << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & |
| 2468 | ENA_REGS_DEV_CTL_RESET_REASON_MASK; |
| 2469 | } |
| 2470 | ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); |
| 2471 | |
| 2472 | /* Write again the MMIO read request address */ |
| 2473 | ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); |
| 2474 | |
| 2475 | rc = wait_for_reset_state(ena_dev, timeout, |
no test coverage detected