| 1419 | } |
| 1420 | |
| 1421 | static void |
| 1422 | igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev) |
| 1423 | { |
| 1424 | static const union e1000_adv_tx_desc zeroed_desc = {{0}}; |
| 1425 | struct igb_tx_entry *txe = txq->sw_ring; |
| 1426 | uint16_t i, prev; |
| 1427 | struct e1000_hw *hw; |
| 1428 | |
| 1429 | hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 1430 | /* Zero out HW ring memory */ |
| 1431 | for (i = 0; i < txq->nb_tx_desc; i++) { |
| 1432 | txq->tx_ring[i] = zeroed_desc; |
| 1433 | } |
| 1434 | |
| 1435 | /* Initialize ring entries */ |
| 1436 | prev = (uint16_t)(txq->nb_tx_desc - 1); |
| 1437 | for (i = 0; i < txq->nb_tx_desc; i++) { |
| 1438 | volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]); |
| 1439 | |
| 1440 | txd->wb.status = E1000_TXD_STAT_DD; |
| 1441 | txe[i].mbuf = NULL; |
| 1442 | txe[i].last_id = i; |
| 1443 | txe[prev].next_id = i; |
| 1444 | prev = i; |
| 1445 | } |
| 1446 | |
| 1447 | txq->txd_type = E1000_ADVTXD_DTYP_DATA; |
| 1448 | /* 82575 specific, each tx queue will use 2 hw contexts */ |
| 1449 | if (hw->mac.type == e1000_82575) |
| 1450 | txq->ctx_start = txq->queue_id * IGB_CTX_NUM; |
| 1451 | |
| 1452 | igb_reset_tx_queue_stat(txq); |
| 1453 | } |
| 1454 | |
| 1455 | uint64_t |
| 1456 | igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev) |
no test coverage detected