| 3272 | } |
| 3273 | |
| 3274 | static void |
| 3275 | igbvf_stop_adapter(struct rte_eth_dev *dev) |
| 3276 | { |
| 3277 | u32 reg_val; |
| 3278 | u16 i; |
| 3279 | struct rte_eth_dev_info dev_info; |
| 3280 | struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 3281 | int ret; |
| 3282 | |
| 3283 | memset(&dev_info, 0, sizeof(dev_info)); |
| 3284 | ret = eth_igbvf_infos_get(dev, &dev_info); |
| 3285 | if (ret != 0) |
| 3286 | return; |
| 3287 | |
| 3288 | /* Clear interrupt mask to stop from interrupts being generated */ |
| 3289 | igbvf_intr_disable(hw); |
| 3290 | |
| 3291 | /* Clear any pending interrupts, flush previous writes */ |
| 3292 | E1000_READ_REG(hw, E1000_EICR); |
| 3293 | |
| 3294 | /* Disable the transmit unit. Each queue must be disabled. */ |
| 3295 | for (i = 0; i < dev_info.max_tx_queues; i++) |
| 3296 | E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH); |
| 3297 | |
| 3298 | /* Disable the receive unit by stopping each queue */ |
| 3299 | for (i = 0; i < dev_info.max_rx_queues; i++) { |
| 3300 | reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i)); |
| 3301 | reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE; |
| 3302 | E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val); |
| 3303 | while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE) |
| 3304 | ; |
| 3305 | } |
| 3306 | |
| 3307 | /* flush all queues disables */ |
| 3308 | E1000_WRITE_FLUSH(hw); |
| 3309 | msec_delay(2); |
| 3310 | } |
| 3311 | |
| 3312 | static int eth_igbvf_link_update(struct e1000_hw *hw) |
| 3313 | { |
no test coverage detected