Function ring_tx_db

dpdk/drivers/net/cxgbe/sge.c:618–674

* ring_tx_db - ring a Tx queue's doorbell * @adap: the adapter * @q: the Tx queue * @n: number of new descriptors to give to HW * * Ring the doorbell for a Tx queue. */

 * Ring the doorbell for a Tx queue.
 */
static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q)
{
	int n = Q_IDXDIFF(q, dbidx);

	/*
	 * Make sure that all writes to the TX Descriptors are committed
	 * before we tell the hardware about them.
	 */
	rte_wmb();

	/*
	 * If we don't have access to the new User Doorbell (T5+), use the old
	 * doorbell mechanism; otherwise use the new BAR2 mechanism.
	 */
	if (unlikely(!q->bar2_addr)) {
		u32 val = V_PIDX(n);

		/*
		 * For T4 we need to participate in the Doorbell Recovery
		 * mechanism.
		 */
		if (!q->db_disabled)
			t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
				     V_QID(q->cntxt_id) | val);
		else
			q->db_pidx_inc += n;
		q->db_pidx = q->pidx;
	} else {
		u32 val = V_PIDX_T5(n);

		/*
		 * T4 and later chips share the same PIDX field offset within
		 * the doorbell, but T5 and later shrank the field in order to
		 * gain a bit for Doorbell Priority.  The field was absurdly
		 * large in the first place (14 bits) so we just use the T5
		 * and later limits and warn if a Queue ID is too large.
		 */
		WARN_ON(val & F_DBPRIO);

		writel(val | V_QID(q->bar2_qid),
		       (void *)((uintptr_t)q->bar2_addr + SGE_UDB_KDOORBELL));

		/*
		 * This Write Memory Barrier will force the write to the User
		 * Doorbell area to be flushed.  This is needed to prevent
		 * writes on different CPUs for the same queue from hitting
		 * the adapter out of order.  This is required when some Work
		 * Requests take the Write Combine Gather Buffer path (user
		 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
		 * take the traditional path where we simply increment the
		 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
		 * hardware DMA read the actual Work Request.
		 */
		rte_wmb();
	}
	q->dbidx = q->pidx;
}