Function cxgbe_poll

dpdk/drivers/net/cxgbe/sge.c:1629–1673

}

int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
	       unsigned int budget, unsigned int *work_done)
{
	struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
	unsigned int cidx_inc;
	unsigned int params;
	u32 val;

	if (unlikely(rxq->flags & IQ_STOPPED)) {
		*work_done = 0;
		return 0;
	}

	*work_done = process_responses(q, budget, rx_pkts);

	if (*work_done) {
		cidx_inc = R_IDXDIFF(q, gts_idx);

		if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 64)
			__refill_fl(q->adapter, &rxq->fl);

		params = q->intr_params;
		q->next_intr_params = params;
		val = V_CIDXINC(cidx_inc) | V_SEINTARM(params);

		if (unlikely(!q->bar2_addr)) {
			u32 reg = is_pf4(q->adapter) ? MYPF_REG(A_SGE_PF_GTS) :
						       T4VF_SGE_BASE_ADDR +
						       A_SGE_VF_GTS;

			t4_write_reg(q->adapter, reg,
				     val | V_INGRESSQID((u32)q->cntxt_id));
		} else {
			writel(val | V_INGRESSQID(q->bar2_qid),
			       (void *)((uintptr_t)q->bar2_addr + SGE_UDB_GTS));
			/* This Write memory Barrier will force the
			 * write to the User Doorbell area to be
			 * flushed.
			 */
			wmb();
		}
		q->gts_idx = q->cidx;
	}
	return 0;
}

/**
 * bar2_address - return the BAR2 address for an SGE Queue's Registers