* t4_fixup_host_params_compat - fix up host-dependent parameters * @adap: the adapter * @page_size: the host's Base Page Size * @cache_line_size: the host's Cache Line Size * @chip_compat: maintain compatibility with designated chip * * Various registers in the chip contain values which are dependent on the * host's Base Page and Cache Line Sizes. This function will fix all of * those reg
| 3504 | * the drivers haven't [yet] been updated with new chip support. |
| 3505 | */ |
| 3506 | int t4_fixup_host_params_compat(struct adapter *adap, |
| 3507 | unsigned int page_size, |
| 3508 | unsigned int cache_line_size, |
| 3509 | enum chip_type chip_compat) |
| 3510 | { |
| 3511 | unsigned int page_shift = cxgbe_fls(page_size) - 1; |
| 3512 | unsigned int sge_hps = page_shift - 10; |
| 3513 | unsigned int stat_len = cache_line_size > 64 ? 128 : 64; |
| 3514 | unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; |
| 3515 | unsigned int fl_align_log = cxgbe_fls(fl_align) - 1; |
| 3516 | |
| 3517 | t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE, |
| 3518 | V_HOSTPAGESIZEPF0(sge_hps) | |
| 3519 | V_HOSTPAGESIZEPF1(sge_hps) | |
| 3520 | V_HOSTPAGESIZEPF2(sge_hps) | |
| 3521 | V_HOSTPAGESIZEPF3(sge_hps) | |
| 3522 | V_HOSTPAGESIZEPF4(sge_hps) | |
| 3523 | V_HOSTPAGESIZEPF5(sge_hps) | |
| 3524 | V_HOSTPAGESIZEPF6(sge_hps) | |
| 3525 | V_HOSTPAGESIZEPF7(sge_hps)); |
| 3526 | |
| 3527 | if (is_t4(adap->params.chip) || is_t4(chip_compat)) |
| 3528 | t4_set_reg_field(adap, A_SGE_CONTROL, |
| 3529 | V_INGPADBOUNDARY(M_INGPADBOUNDARY) | |
| 3530 | F_EGRSTATUSPAGESIZE, |
| 3531 | V_INGPADBOUNDARY(fl_align_log - |
| 3532 | X_INGPADBOUNDARY_SHIFT) | |
| 3533 | V_EGRSTATUSPAGESIZE(stat_len != 64)); |
| 3534 | else { |
| 3535 | unsigned int pack_align; |
| 3536 | unsigned int ingpad, ingpack; |
| 3537 | unsigned int pcie_cap; |
| 3538 | |
| 3539 | /* |
| 3540 | * T5 introduced the separation of the Free List Padding and |
| 3541 | * Packing Boundaries. Thus, we can select a smaller Padding |
| 3542 | * Boundary to avoid uselessly chewing up PCIe Link and Memory |
| 3543 | * Bandwidth, and use a Packing Boundary which is large enough |
| 3544 | * to avoid false sharing between CPUs, etc. |
| 3545 | * |
| 3546 | * For the PCI Link, the smaller the Padding Boundary the |
| 3547 | * better. For the Memory Controller, a smaller Padding |
| 3548 | * Boundary is better until we cross under the Memory Line |
| 3549 | * Size (the minimum unit of transfer to/from Memory). If we |
| 3550 | * have a Padding Boundary which is smaller than the Memory |
| 3551 | * Line Size, that'll involve a Read-Modify-Write cycle on the |
| 3552 | * Memory Controller which is never good. |
| 3553 | */ |
| 3554 | |
| 3555 | /* We want the Packing Boundary to be based on the Cache Line |
| 3556 | * Size in order to help avoid False Sharing performance |
| 3557 | * issues between CPUs, etc. We also want the Packing |
| 3558 | * Boundary to incorporate the PCI-E Maximum Payload Size. We |
| 3559 | * get best performance when the Packing Boundary is a |
| 3560 | * multiple of the Maximum Payload Size. |
| 3561 | */ |
| 3562 | pack_align = fl_align; |
| 3563 | pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP); |
no test coverage detected