| 4187 | } |
| 4188 | |
| 4189 | static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) |
| 4190 | { |
| 4191 | struct bnxt_error_recovery_info *info = bp->recovery_info; |
| 4192 | uint32_t delay = info->delay_after_reset[index]; |
| 4193 | uint32_t val = info->reset_reg_val[index]; |
| 4194 | uint32_t reg = info->reset_reg[index]; |
| 4195 | uint32_t type, offset; |
| 4196 | int ret; |
| 4197 | |
| 4198 | type = BNXT_FW_STATUS_REG_TYPE(reg); |
| 4199 | offset = BNXT_FW_STATUS_REG_OFF(reg); |
| 4200 | |
| 4201 | switch (type) { |
| 4202 | case BNXT_FW_STATUS_REG_TYPE_CFG: |
| 4203 | ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); |
| 4204 | if (ret < 0) { |
| 4205 | PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", |
| 4206 | val, offset); |
| 4207 | return; |
| 4208 | } |
| 4209 | break; |
| 4210 | case BNXT_FW_STATUS_REG_TYPE_GRC: |
| 4211 | offset = bnxt_map_reset_regs(bp, offset); |
| 4212 | rte_write32(val, (uint8_t *)bp->bar0 + offset); |
| 4213 | break; |
| 4214 | case BNXT_FW_STATUS_REG_TYPE_BAR0: |
| 4215 | rte_write32(val, (uint8_t *)bp->bar0 + offset); |
| 4216 | break; |
| 4217 | } |
| 4218 | /* wait on a specific interval of time until core reset is complete */ |
| 4219 | if (delay) |
| 4220 | rte_delay_ms(delay); |
| 4221 | } |
| 4222 | |
| 4223 | static void bnxt_dev_cleanup(struct bnxt *bp) |
| 4224 | { |
no test coverage detected