| 4493 | } |
| 4494 | |
| 4495 | uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) |
| 4496 | { |
| 4497 | struct bnxt_error_recovery_info *info = bp->recovery_info; |
| 4498 | uint32_t reg = info->status_regs[index]; |
| 4499 | uint32_t type, offset, val = 0; |
| 4500 | int ret = 0; |
| 4501 | |
| 4502 | type = BNXT_FW_STATUS_REG_TYPE(reg); |
| 4503 | offset = BNXT_FW_STATUS_REG_OFF(reg); |
| 4504 | |
| 4505 | switch (type) { |
| 4506 | case BNXT_FW_STATUS_REG_TYPE_CFG: |
| 4507 | ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); |
| 4508 | if (ret < 0) |
| 4509 | PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x", |
| 4510 | offset); |
| 4511 | break; |
| 4512 | case BNXT_FW_STATUS_REG_TYPE_GRC: |
| 4513 | offset = info->mapped_status_regs[index]; |
| 4514 | /* FALLTHROUGH */ |
| 4515 | case BNXT_FW_STATUS_REG_TYPE_BAR0: |
| 4516 | val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + |
| 4517 | offset)); |
| 4518 | break; |
| 4519 | } |
| 4520 | |
| 4521 | return val; |
| 4522 | } |
| 4523 | |
| 4524 | static int bnxt_fw_reset_all(struct bnxt *bp) |
| 4525 | { |
no test coverage detected