| 4456 | } |
| 4457 | |
| 4458 | void bnxt_dev_reset_and_resume(void *arg) |
| 4459 | { |
| 4460 | struct bnxt *bp = arg; |
| 4461 | uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; |
| 4462 | uint16_t val = 0; |
| 4463 | int rc; |
| 4464 | |
| 4465 | bnxt_dev_cleanup(bp); |
| 4466 | PMD_DRV_LOG(INFO, "Port: %u Finished bnxt_dev_cleanup\n", |
| 4467 | bp->eth_dev->data->port_id); |
| 4468 | |
| 4469 | bnxt_wait_for_device_shutdown(bp); |
| 4470 | |
| 4471 | /* During some fatal firmware error conditions, the PCI config space |
| 4472 | * register 0x2e which normally contains the subsystem ID will become |
| 4473 | * 0xffff. This register will revert back to the normal value after |
| 4474 | * the chip has completed core reset. If we detect this condition, |
| 4475 | * we can poll this config register immediately for the value to revert. |
| 4476 | */ |
| 4477 | if (bp->flags & BNXT_FLAG_FATAL_ERROR) { |
| 4478 | rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); |
| 4479 | if (rc < 0) { |
| 4480 | PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); |
| 4481 | return; |
| 4482 | } |
| 4483 | if (val == 0xffff) { |
| 4484 | bp->fw_reset_min_msecs = 0; |
| 4485 | us = 1; |
| 4486 | } |
| 4487 | } |
| 4488 | |
| 4489 | rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); |
| 4490 | if (rc) |
| 4491 | PMD_DRV_LOG(ERR, "Port %u: Error setting recovery alarm", |
| 4492 | bp->eth_dev->data->port_id); |
| 4493 | } |
| 4494 | |
| 4495 | uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) |
| 4496 | { |
nothing calls this directly
no test coverage detected