| 4231 | } |
| 4232 | |
| 4233 | static int |
| 4234 | bnxt_check_fw_reset_done(struct bnxt *bp) |
| 4235 | { |
| 4236 | int timeout = bp->fw_reset_max_msecs; |
| 4237 | uint16_t val = 0; |
| 4238 | int rc; |
| 4239 | |
| 4240 | do { |
| 4241 | rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); |
| 4242 | if (rc < 0) { |
| 4243 | PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); |
| 4244 | return rc; |
| 4245 | } |
| 4246 | if (val != 0xffff) |
| 4247 | break; |
| 4248 | rte_delay_ms(1); |
| 4249 | } while (timeout--); |
| 4250 | |
| 4251 | if (val == 0xffff) { |
| 4252 | PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); |
| 4253 | return -1; |
| 4254 | } |
| 4255 | |
| 4256 | return 0; |
| 4257 | } |
| 4258 | |
| 4259 | static int bnxt_restore_vlan_filters(struct bnxt *bp) |
| 4260 | { |
no test coverage detected