| 720 | } |
| 721 | |
| 722 | static int |
| 723 | avp_dev_enable_interrupts(struct rte_eth_dev *eth_dev) |
| 724 | { |
| 725 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); |
| 726 | void *registers = pci_dev->mem_resource[RTE_AVP_PCI_MMIO_BAR].addr; |
| 727 | int ret; |
| 728 | |
| 729 | if (registers == NULL) |
| 730 | return -EINVAL; |
| 731 | |
| 732 | /* enable UIO interrupt handling */ |
| 733 | ret = rte_intr_enable(pci_dev->intr_handle); |
| 734 | if (ret < 0) { |
| 735 | PMD_DRV_LOG(ERR, "Failed to enable UIO interrupts, ret=%d\n", |
| 736 | ret); |
| 737 | return ret; |
| 738 | } |
| 739 | |
| 740 | /* inform the device that all interrupts are enabled */ |
| 741 | AVP_WRITE32(RTE_AVP_APP_INTERRUPTS_MASK, |
| 742 | RTE_PTR_ADD(registers, RTE_AVP_INTERRUPT_MASK_OFFSET)); |
| 743 | |
| 744 | return 0; |
| 745 | } |
| 746 | |
| 747 | static int |
| 748 | avp_dev_disable_interrupts(struct rte_eth_dev *eth_dev) |
no test coverage detected