| 323 | |
| 324 | |
| 325 | static int |
| 326 | atomic_basic(struct test *t) |
| 327 | { |
| 328 | const uint8_t rx_port = 0; |
| 329 | const uint8_t w1_port = 1; |
| 330 | const uint8_t w3_port = 3; |
| 331 | const uint8_t tx_port = 4; |
| 332 | int err; |
| 333 | int i; |
| 334 | uint32_t deq_pkts; |
| 335 | struct rte_mbuf *mbufs[3]; |
| 336 | const uint32_t MAGIC_SEQN = 1234; |
| 337 | |
| 338 | /* Create instance with 5 ports */ |
| 339 | if (init(t, 2, tx_port+1) < 0 || |
| 340 | create_ports(t, tx_port+1) < 0 || |
| 341 | create_queues_type(t, 2, OPDL_Q_TYPE_ATOMIC)) { |
| 342 | PMD_DRV_LOG(ERR, "%d: Error initializing device", __LINE__); |
| 343 | return -1; |
| 344 | } |
| 345 | |
| 346 | |
| 347 | /* |
| 348 | * CQ mapping to QID |
| 349 | * We need three ports, all mapped to the same ordered qid0. Then we'll |
| 350 | * take a packet out to each port, re-enqueue in reverse order, |
| 351 | * then make sure the reordering has taken place properly when we |
| 352 | * dequeue from the tx_port. |
| 353 | * |
| 354 | * Simplified test setup diagram: |
| 355 | * |
| 356 | * rx_port w1_port |
| 357 | * \ / \ |
| 358 | * qid0 - w2_port - qid1 |
| 359 | * \ / \ |
| 360 | * w3_port tx_port |
| 361 | */ |
| 362 | /* CQ mapping to QID for Atomic ports (directed mapped on create) */ |
| 363 | for (i = w1_port; i <= w3_port; i++) { |
| 364 | err = rte_event_port_link(evdev, t->port[i], &t->qid[0], NULL, |
| 365 | 1); |
| 366 | if (err != 1) { |
| 367 | PMD_DRV_LOG(ERR, "%d: error mapping lb qid", |
| 368 | __LINE__); |
| 369 | cleanup(t); |
| 370 | return -1; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | err = rte_event_port_link(evdev, t->port[tx_port], &t->qid[1], NULL, |
| 375 | 1); |
| 376 | if (err != 1) { |
| 377 | PMD_DRV_LOG(ERR, "%d: error mapping TX qid", __LINE__); |
| 378 | cleanup(t); |
| 379 | return -1; |
| 380 | } |
| 381 | |
| 382 | if (rte_event_dev_start(evdev) < 0) { |
no test coverage detected