| 165 | } |
| 166 | |
| 167 | int |
| 168 | vf_get_vf_config_mode(uint8_t *bar_addr) |
| 169 | { |
| 170 | union aqmq_qsz aqmq_qsz; |
| 171 | uint64_t reg_addr; |
| 172 | int q, vf_mode; |
| 173 | |
| 174 | aqmq_qsz.u64 = 0; |
| 175 | aqmq_qsz.s.host_queue_size = 0xDEADBEEF; |
| 176 | reg_addr = AQMQ_QSZX(0); |
| 177 | nitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64); |
| 178 | rte_delay_us_block(CSR_DELAY); |
| 179 | |
| 180 | aqmq_qsz.u64 = 0; |
| 181 | for (q = 1; q < MAX_VF_QUEUES; q++) { |
| 182 | reg_addr = AQMQ_QSZX(q); |
| 183 | aqmq_qsz.u64 = nitrox_read_csr(bar_addr, reg_addr); |
| 184 | if (aqmq_qsz.s.host_queue_size == 0xDEADBEEF) |
| 185 | break; |
| 186 | } |
| 187 | |
| 188 | switch (q) { |
| 189 | case 1: |
| 190 | vf_mode = NITROX_MODE_VF128; |
| 191 | break; |
| 192 | case 2: |
| 193 | vf_mode = NITROX_MODE_VF64; |
| 194 | break; |
| 195 | case 4: |
| 196 | vf_mode = NITROX_MODE_VF32; |
| 197 | break; |
| 198 | case 8: |
| 199 | vf_mode = NITROX_MODE_VF16; |
| 200 | break; |
| 201 | default: |
| 202 | vf_mode = 0; |
| 203 | break; |
| 204 | } |
| 205 | |
| 206 | return vf_mode; |
| 207 | } |
| 208 | |
| 209 | int |
| 210 | vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode) |
no test coverage detected