| 16 | #define NITROX_COUNT_THOLD 0xFFFFFFFF |
| 17 | |
| 18 | void |
| 19 | nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring) |
| 20 | { |
| 21 | union nps_pkt_in_instr_ctl pkt_in_instr_ctl; |
| 22 | uint64_t reg_addr; |
| 23 | int max_retries = 5; |
| 24 | |
| 25 | reg_addr = NPS_PKT_IN_INSTR_CTLX(ring); |
| 26 | pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); |
| 27 | pkt_in_instr_ctl.s.enb = 0; |
| 28 | nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_ctl.u64); |
| 29 | rte_delay_us_block(100); |
| 30 | |
| 31 | /* wait for enable bit to be cleared */ |
| 32 | pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); |
| 33 | while (pkt_in_instr_ctl.s.enb && max_retries--) { |
| 34 | rte_delay_ms(10); |
| 35 | pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); |
| 36 | } |
| 37 | } |
| 38 | |
| 39 | void |
| 40 | nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port) |
no test coverage detected