| 2874 | } |
| 2875 | |
| 2876 | int |
| 2877 | process_ops_to_dequeue(struct ccp_qp *qp, |
| 2878 | struct rte_crypto_op **op, |
| 2879 | uint16_t nb_ops, |
| 2880 | uint16_t *total_nb_ops) |
| 2881 | { |
| 2882 | struct ccp_batch_info *b_info; |
| 2883 | uint32_t cur_head_offset; |
| 2884 | |
| 2885 | if (qp->b_info != NULL) { |
| 2886 | b_info = qp->b_info; |
| 2887 | if (unlikely(b_info->op_idx > 0)) |
| 2888 | goto success; |
| 2889 | } else if (rte_ring_dequeue(qp->processed_pkts, |
| 2890 | (void **)&b_info)) |
| 2891 | return 0; |
| 2892 | |
| 2893 | if (b_info->auth_ctr == b_info->opcnt) |
| 2894 | goto success; |
| 2895 | *total_nb_ops = b_info->total_nb_ops; |
| 2896 | cur_head_offset = CCP_READ_REG(b_info->cmd_q->reg_base, |
| 2897 | CMD_Q_HEAD_LO_BASE); |
| 2898 | |
| 2899 | if (b_info->head_offset < b_info->tail_offset) { |
| 2900 | if ((cur_head_offset >= b_info->head_offset) && |
| 2901 | (cur_head_offset < b_info->tail_offset)) { |
| 2902 | qp->b_info = b_info; |
| 2903 | return 0; |
| 2904 | } |
| 2905 | } else if (b_info->tail_offset != b_info->head_offset) { |
| 2906 | if ((cur_head_offset >= b_info->head_offset) || |
| 2907 | (cur_head_offset < b_info->tail_offset)) { |
| 2908 | qp->b_info = b_info; |
| 2909 | return 0; |
| 2910 | } |
| 2911 | } |
| 2912 | |
| 2913 | |
| 2914 | success: |
| 2915 | *total_nb_ops = b_info->total_nb_ops; |
| 2916 | nb_ops = ccp_prepare_ops(qp, op, b_info, nb_ops); |
| 2917 | rte_atomic64_add(&b_info->cmd_q->free_slots, b_info->desccnt); |
| 2918 | b_info->desccnt = 0; |
| 2919 | if (b_info->opcnt > 0) { |
| 2920 | qp->b_info = b_info; |
| 2921 | } else { |
| 2922 | rte_mempool_put(qp->batch_mp, (void *)b_info); |
| 2923 | qp->b_info = NULL; |
| 2924 | } |
| 2925 | |
| 2926 | return nb_ops; |
| 2927 | } |
no test coverage detected