* Ring a doorbell and flush the update if requested. * * @param uar * Pointer to UAR data structure. * @param val * value to write in big endian format. * @param index * Index of doorbell record. * @param db_rec * Address of doorbell record. * @param flash * Decide whether to flush the DB writing using a memory barrier. */
| 400 | * Decide whether to flush the DB writing using a memory barrier. |
| 401 | */ |
| 402 | static __rte_always_inline void |
| 403 | mlx5_doorbell_ring(struct mlx5_uar_data *uar, uint64_t val, uint32_t index, |
| 404 | volatile uint32_t *db_rec, bool flash) |
| 405 | { |
| 406 | rte_io_wmb(); |
| 407 | *db_rec = rte_cpu_to_be_32(index); |
| 408 | /* Ensure ordering between DB record actual update and UAR access. */ |
| 409 | rte_wmb(); |
| 410 | #ifdef RTE_ARCH_64 |
| 411 | *uar->db = val; |
| 412 | #else /* !RTE_ARCH_64 */ |
| 413 | rte_spinlock_lock(uar->sl_p); |
| 414 | *(volatile uint32_t *)uar->db = val; |
| 415 | rte_io_wmb(); |
| 416 | *((volatile uint32_t *)uar->db + 1) = val >> 32; |
| 417 | rte_spinlock_unlock(uar->sl_p); |
| 418 | #endif |
| 419 | if (flash) |
| 420 | rte_wmb(); |
| 421 | } |
| 422 | |
| 423 | /** |
| 424 | * Get the doorbell register mapping type. |
no test coverage detected