* idpf_init_hw - main initialization routine * @hw: pointer to the hardware structure * @ctlq_size: struct to pass ctlq size data */
| 47 | * @ctlq_size: struct to pass ctlq size data |
| 48 | */ |
| 49 | int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) |
| 50 | { |
| 51 | struct idpf_ctlq_create_info *q_info; |
| 52 | int status = 0; |
| 53 | struct idpf_ctlq_info *cq = NULL; |
| 54 | |
| 55 | /* Setup initial control queues */ |
| 56 | q_info = (struct idpf_ctlq_create_info *) |
| 57 | idpf_calloc(hw, 2, sizeof(struct idpf_ctlq_create_info)); |
| 58 | if (!q_info) |
| 59 | return -ENOMEM; |
| 60 | |
| 61 | q_info[0].type = IDPF_CTLQ_TYPE_MAILBOX_TX; |
| 62 | q_info[0].buf_size = ctlq_size.asq_buf_size; |
| 63 | q_info[0].len = ctlq_size.asq_ring_size; |
| 64 | q_info[0].id = -1; /* default queue */ |
| 65 | |
| 66 | if (hw->mac.type == IDPF_MAC_PF) { |
| 67 | q_info[0].reg.head = PF_FW_ATQH; |
| 68 | q_info[0].reg.tail = PF_FW_ATQT; |
| 69 | q_info[0].reg.len = PF_FW_ATQLEN; |
| 70 | q_info[0].reg.bah = PF_FW_ATQBAH; |
| 71 | q_info[0].reg.bal = PF_FW_ATQBAL; |
| 72 | q_info[0].reg.len_mask = PF_FW_ATQLEN_ATQLEN_M; |
| 73 | q_info[0].reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; |
| 74 | q_info[0].reg.head_mask = PF_FW_ATQH_ATQH_M; |
| 75 | } else { |
| 76 | q_info[0].reg.head = VF_ATQH; |
| 77 | q_info[0].reg.tail = VF_ATQT; |
| 78 | q_info[0].reg.len = VF_ATQLEN; |
| 79 | q_info[0].reg.bah = VF_ATQBAH; |
| 80 | q_info[0].reg.bal = VF_ATQBAL; |
| 81 | q_info[0].reg.len_mask = VF_ATQLEN_ATQLEN_M; |
| 82 | q_info[0].reg.len_ena_mask = VF_ATQLEN_ATQENABLE_M; |
| 83 | q_info[0].reg.head_mask = VF_ATQH_ATQH_M; |
| 84 | } |
| 85 | |
| 86 | q_info[1].type = IDPF_CTLQ_TYPE_MAILBOX_RX; |
| 87 | q_info[1].buf_size = ctlq_size.arq_buf_size; |
| 88 | q_info[1].len = ctlq_size.arq_ring_size; |
| 89 | q_info[1].id = -1; /* default queue */ |
| 90 | |
| 91 | if (hw->mac.type == IDPF_MAC_PF) { |
| 92 | q_info[1].reg.head = PF_FW_ARQH; |
| 93 | q_info[1].reg.tail = PF_FW_ARQT; |
| 94 | q_info[1].reg.len = PF_FW_ARQLEN; |
| 95 | q_info[1].reg.bah = PF_FW_ARQBAH; |
| 96 | q_info[1].reg.bal = PF_FW_ARQBAL; |
| 97 | q_info[1].reg.len_mask = PF_FW_ARQLEN_ARQLEN_M; |
| 98 | q_info[1].reg.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M; |
| 99 | q_info[1].reg.head_mask = PF_FW_ARQH_ARQH_M; |
| 100 | } else { |
| 101 | q_info[1].reg.head = VF_ARQH; |
| 102 | q_info[1].reg.tail = VF_ARQT; |
| 103 | q_info[1].reg.len = VF_ARQLEN; |
| 104 | q_info[1].reg.bah = VF_ARQBAH; |
| 105 | q_info[1].reg.bal = VF_ARQBAL; |
| 106 | q_info[1].reg.len_mask = VF_ARQLEN_ARQLEN_M; |
nothing calls this directly
no test coverage detected