| 591 | } |
| 592 | |
| 593 | static int |
| 594 | test_lpm_perf(void) |
| 595 | { |
| 596 | struct rte_lpm_config config; |
| 597 | |
| 598 | config.max_rules = 2000000; |
| 599 | config.number_tbl8s = 2048; |
| 600 | config.flags = 0; |
| 601 | uint64_t begin, total_time, lpm_used_entries = 0; |
| 602 | unsigned i, j; |
| 603 | uint32_t next_hop_add = 0xAA, next_hop_return = 0; |
| 604 | int status = 0; |
| 605 | uint64_t cache_line_counter = 0; |
| 606 | int64_t count = 0; |
| 607 | |
| 608 | rte_srand(rte_rdtsc()); |
| 609 | |
| 610 | generate_large_route_rule_table(); |
| 611 | |
| 612 | printf("No. routes = %u\n", (unsigned) NUM_ROUTE_ENTRIES); |
| 613 | |
| 614 | print_route_distribution(large_route_table, (uint32_t) NUM_ROUTE_ENTRIES); |
| 615 | |
| 616 | lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config); |
| 617 | TEST_LPM_ASSERT(lpm != NULL); |
| 618 | |
| 619 | /* Measure add. */ |
| 620 | begin = rte_rdtsc(); |
| 621 | |
| 622 | for (i = 0; i < NUM_ROUTE_ENTRIES; i++) { |
| 623 | if (rte_lpm_add(lpm, large_route_table[i].ip, |
| 624 | large_route_table[i].depth, next_hop_add) == 0) |
| 625 | status++; |
| 626 | } |
| 627 | /* End Timer. */ |
| 628 | total_time = rte_rdtsc() - begin; |
| 629 | |
| 630 | printf("Unique added entries = %d\n", status); |
| 631 | /* Obtain add statistics. */ |
| 632 | for (i = 0; i < RTE_LPM_TBL24_NUM_ENTRIES; i++) { |
| 633 | if (lpm->tbl24[i].valid) |
| 634 | lpm_used_entries++; |
| 635 | |
| 636 | if (i % 32 == 0) { |
| 637 | if ((uint64_t)count < lpm_used_entries) { |
| 638 | cache_line_counter++; |
| 639 | count = lpm_used_entries; |
| 640 | } |
| 641 | } |
| 642 | } |
| 643 | |
| 644 | printf("Used table 24 entries = %u (%g%%)\n", |
| 645 | (unsigned) lpm_used_entries, |
| 646 | (lpm_used_entries * 100.0) / RTE_LPM_TBL24_NUM_ENTRIES); |
| 647 | printf("64 byte Cache entries used = %u (%u bytes)\n", |
| 648 | (unsigned) cache_line_counter, (unsigned) cache_line_counter * 64); |
| 649 | |
| 650 | printf("Average LPM Add: %g cycles\n", |
nothing calls this directly
no test coverage detected