| 55 | static uint64_t gwrites; |
| 56 | |
| 57 | static int |
| 58 | test_hash_readwrite_worker(__rte_unused void *arg) |
| 59 | { |
| 60 | uint64_t i, offset; |
| 61 | uint32_t lcore_id = rte_lcore_id(); |
| 62 | uint64_t begin, cycles; |
| 63 | int *ret; |
| 64 | |
| 65 | ret = rte_malloc(NULL, sizeof(int) * |
| 66 | tbl_rw_test_param.num_insert, 0); |
| 67 | for (i = 0; i < rte_lcore_count(); i++) { |
| 68 | if (worker_core_ids[i] == lcore_id) |
| 69 | break; |
| 70 | } |
| 71 | offset = tbl_rw_test_param.num_insert * i; |
| 72 | |
| 73 | printf("Core #%d inserting and reading %d: %'"PRId64" - %'"PRId64"\n", |
| 74 | lcore_id, tbl_rw_test_param.num_insert, |
| 75 | offset, offset + tbl_rw_test_param.num_insert - 1); |
| 76 | |
| 77 | begin = rte_rdtsc_precise(); |
| 78 | |
| 79 | for (i = offset; i < offset + tbl_rw_test_param.num_insert; i++) { |
| 80 | |
| 81 | if (rte_hash_lookup(tbl_rw_test_param.h, |
| 82 | tbl_rw_test_param.keys + i) > 0) |
| 83 | break; |
| 84 | |
| 85 | ret[i - offset] = rte_hash_add_key(tbl_rw_test_param.h, |
| 86 | tbl_rw_test_param.keys + i); |
| 87 | if (ret[i - offset] < 0) |
| 88 | break; |
| 89 | |
| 90 | /* lookup a random key */ |
| 91 | uint32_t rand = rte_rand() % (i + 1 - offset); |
| 92 | |
| 93 | if (rte_hash_lookup(tbl_rw_test_param.h, |
| 94 | tbl_rw_test_param.keys + rand) != ret[rand]) |
| 95 | break; |
| 96 | |
| 97 | |
| 98 | if (rte_hash_del_key(tbl_rw_test_param.h, |
| 99 | tbl_rw_test_param.keys + rand) != ret[rand]) |
| 100 | break; |
| 101 | |
| 102 | ret[rand] = rte_hash_add_key(tbl_rw_test_param.h, |
| 103 | tbl_rw_test_param.keys + rand); |
| 104 | if (ret[rand] < 0) |
| 105 | break; |
| 106 | |
| 107 | if (rte_hash_lookup(tbl_rw_test_param.h, |
| 108 | tbl_rw_test_param.keys + rand) != ret[rand]) |
| 109 | break; |
| 110 | } |
| 111 | |
| 112 | cycles = rte_rdtsc_precise() - begin; |
| 113 | __atomic_fetch_add(&gcycles, cycles, __ATOMIC_RELAXED); |
| 114 | __atomic_fetch_add(&ginsertions, i - offset, __ATOMIC_RELAXED); |
nothing calls this directly
no test coverage detected