| 49 | static int use_htm; |
| 50 | |
| 51 | static int |
| 52 | test_hash_multiwriter_worker(void *arg) |
| 53 | { |
| 54 | uint64_t i, offset; |
| 55 | uint16_t pos_core; |
| 56 | uint32_t lcore_id = rte_lcore_id(); |
| 57 | uint64_t begin, cycles; |
| 58 | uint16_t *enabled_core_ids = (uint16_t *)arg; |
| 59 | |
| 60 | for (pos_core = 0; pos_core < rte_lcore_count(); pos_core++) { |
| 61 | if (enabled_core_ids[pos_core] == lcore_id) |
| 62 | break; |
| 63 | } |
| 64 | |
| 65 | /* |
| 66 | * Calculate offset for entries based on the position of the |
| 67 | * logical core, from the main core (not counting not enabled cores) |
| 68 | */ |
| 69 | offset = pos_core * tbl_multiwriter_test_params.nb_tsx_insertion; |
| 70 | |
| 71 | printf("Core #%d inserting %d: %'"PRId64" - %'"PRId64"\n", |
| 72 | lcore_id, tbl_multiwriter_test_params.nb_tsx_insertion, |
| 73 | offset, |
| 74 | offset + tbl_multiwriter_test_params.nb_tsx_insertion - 1); |
| 75 | |
| 76 | begin = rte_rdtsc_precise(); |
| 77 | |
| 78 | for (i = offset; |
| 79 | i < offset + tbl_multiwriter_test_params.nb_tsx_insertion; |
| 80 | i++) { |
| 81 | if (rte_hash_add_key(tbl_multiwriter_test_params.h, |
| 82 | tbl_multiwriter_test_params.keys + i) < 0) |
| 83 | break; |
| 84 | } |
| 85 | |
| 86 | cycles = rte_rdtsc_precise() - begin; |
| 87 | __atomic_fetch_add(&gcycles, cycles, __ATOMIC_RELAXED); |
| 88 | __atomic_fetch_add(&ginsertions, i - offset, __ATOMIC_RELAXED); |
| 89 | |
| 90 | for (; i < offset + tbl_multiwriter_test_params.nb_tsx_insertion; i++) |
| 91 | tbl_multiwriter_test_params.keys[i] |
| 92 | = RTE_APP_TEST_HASH_MULTIWRITER_FAILED; |
| 93 | |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | |
| 98 | static int |
nothing calls this directly
no test coverage detected