| 487 | } |
| 488 | |
| 489 | static int |
| 490 | test_dma_completed_status(void) |
| 491 | { |
| 492 | enum rte_dma_status_code status[1] = { 1 }; |
| 493 | uint16_t last_idx = 1; |
| 494 | uint16_t cpl_ret, i; |
| 495 | int ret; |
| 496 | |
| 497 | /* Setup one vchan for later test */ |
| 498 | ret = setup_one_vchan(); |
| 499 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret); |
| 500 | |
| 501 | ret = rte_dma_start(test_dev_id); |
| 502 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret); |
| 503 | |
| 504 | /* Check for enqueue with submit */ |
| 505 | ret = rte_dma_copy(test_dev_id, 0, |
| 506 | rte_malloc_virt2iova(src), |
| 507 | rte_malloc_virt2iova(dst), |
| 508 | TEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT); |
| 509 | RTE_TEST_ASSERT_EQUAL(ret, 0, "Failed to enqueue copy, %d", ret); |
| 510 | rte_delay_us_sleep(TEST_WAIT_US_VAL); |
| 511 | cpl_ret = rte_dma_completed_status(test_dev_id, 0, 1, &last_idx, |
| 512 | status); |
| 513 | RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to completed status"); |
| 514 | RTE_TEST_ASSERT_EQUAL(last_idx, 0, "Last idx should be zero, %u", |
| 515 | last_idx); |
| 516 | for (i = 0; i < RTE_DIM(status); i++) |
| 517 | RTE_TEST_ASSERT_EQUAL(status[i], 0, |
| 518 | "Failed to completed status, %d", status[i]); |
| 519 | |
| 520 | /* Check do completed status again */ |
| 521 | cpl_ret = rte_dma_completed_status(test_dev_id, 0, 1, &last_idx, |
| 522 | status); |
| 523 | RTE_TEST_ASSERT_EQUAL(cpl_ret, 0, "Failed to completed status"); |
| 524 | |
| 525 | /* Check for enqueue with submit again */ |
| 526 | ret = rte_dma_copy(test_dev_id, 0, |
| 527 | rte_malloc_virt2iova(src), |
| 528 | rte_malloc_virt2iova(dst), |
| 529 | TEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT); |
| 530 | RTE_TEST_ASSERT_EQUAL(ret, 1, "Failed to enqueue copy, %d", ret); |
| 531 | rte_delay_us_sleep(TEST_WAIT_US_VAL); |
| 532 | cpl_ret = rte_dma_completed_status(test_dev_id, 0, 1, &last_idx, |
| 533 | status); |
| 534 | RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to completed status"); |
| 535 | RTE_TEST_ASSERT_EQUAL(last_idx, 1, "Last idx should be 1, %u", |
| 536 | last_idx); |
| 537 | for (i = 0; i < RTE_DIM(status); i++) |
| 538 | RTE_TEST_ASSERT_EQUAL(status[i], 0, |
| 539 | "Failed to completed status, %d", status[i]); |
| 540 | |
| 541 | /* Stop dmadev to make sure dmadev to a known state */ |
| 542 | ret = rte_dma_stop(test_dev_id); |
| 543 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret); |
| 544 | |
| 545 | return TEST_SUCCESS; |
| 546 | } |
nothing calls this directly
no test coverage detected