| 424 | } |
| 425 | |
| 426 | static int |
| 427 | test_dma_completed(void) |
| 428 | { |
| 429 | uint16_t last_idx = 1; |
| 430 | bool has_error = true; |
| 431 | uint16_t cpl_ret; |
| 432 | int ret; |
| 433 | |
| 434 | /* Setup one vchan for later test */ |
| 435 | ret = setup_one_vchan(); |
| 436 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret); |
| 437 | |
| 438 | ret = rte_dma_start(test_dev_id); |
| 439 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret); |
| 440 | |
| 441 | setup_memory(); |
| 442 | |
| 443 | /* Check enqueue without submit */ |
| 444 | ret = rte_dma_copy(test_dev_id, 0, |
| 445 | rte_malloc_virt2iova(src), |
| 446 | rte_malloc_virt2iova(dst), |
| 447 | TEST_MEMCPY_SIZE, 0); |
| 448 | RTE_TEST_ASSERT_EQUAL(ret, 0, "Failed to enqueue copy, %d", ret); |
| 449 | rte_delay_us_sleep(TEST_WAIT_US_VAL); |
| 450 | cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error); |
| 451 | RTE_TEST_ASSERT_EQUAL(cpl_ret, 0, "Failed to get completed"); |
| 452 | |
| 453 | /* Check add submit */ |
| 454 | ret = rte_dma_submit(test_dev_id, 0); |
| 455 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to submit, %d", ret); |
| 456 | rte_delay_us_sleep(TEST_WAIT_US_VAL); |
| 457 | cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error); |
| 458 | RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to get completed"); |
| 459 | RTE_TEST_ASSERT_EQUAL(last_idx, 0, "Last idx should be zero, %u", |
| 460 | last_idx); |
| 461 | RTE_TEST_ASSERT_EQUAL(has_error, false, "Should have no error"); |
| 462 | ret = verify_memory(); |
| 463 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory"); |
| 464 | |
| 465 | setup_memory(); |
| 466 | |
| 467 | /* Check for enqueue with submit */ |
| 468 | ret = rte_dma_copy(test_dev_id, 0, |
| 469 | rte_malloc_virt2iova(src), |
| 470 | rte_malloc_virt2iova(dst), |
| 471 | TEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT); |
| 472 | RTE_TEST_ASSERT_EQUAL(ret, 1, "Failed to enqueue copy, %d", ret); |
| 473 | rte_delay_us_sleep(TEST_WAIT_US_VAL); |
| 474 | cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error); |
| 475 | RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to get completed"); |
| 476 | RTE_TEST_ASSERT_EQUAL(last_idx, 1, "Last idx should be 1, %u", |
| 477 | last_idx); |
| 478 | RTE_TEST_ASSERT_EQUAL(has_error, false, "Should have no error"); |
| 479 | ret = verify_memory(); |
| 480 | RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory"); |
| 481 | |
| 482 | /* Stop dmadev to make sure dmadev to a known state */ |
| 483 | ret = rte_dma_stop(test_dev_id); |
nothing calls this directly
no test coverage detected