| 760 | } |
| 761 | |
| 762 | static int |
| 763 | test_burst_capacity(int16_t dev_id, uint16_t vchan) |
| 764 | { |
| 765 | #define CAP_TEST_BURST_SIZE 64 |
| 766 | const int ring_space = rte_dma_burst_capacity(dev_id, vchan); |
| 767 | struct rte_mbuf *src, *dst; |
| 768 | int i, j, iter; |
| 769 | int cap, ret; |
| 770 | bool dma_err; |
| 771 | |
| 772 | src = rte_pktmbuf_alloc(pool); |
| 773 | dst = rte_pktmbuf_alloc(pool); |
| 774 | |
| 775 | /* to test capacity, we enqueue elements and check capacity is reduced |
| 776 | * by one each time - rebaselining the expected value after each burst |
| 777 | * as the capacity is only for a burst. We enqueue multiple bursts to |
| 778 | * fill up half the ring, before emptying it again. We do this multiple |
| 779 | * times to ensure that we get to test scenarios where we get ring |
| 780 | * wrap-around and wrap-around of the ids returned (at UINT16_MAX). |
| 781 | */ |
| 782 | for (iter = 0; iter < 2 * (((int)UINT16_MAX + 1) / ring_space); iter++) { |
| 783 | for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { |
| 784 | cap = rte_dma_burst_capacity(dev_id, vchan); |
| 785 | |
| 786 | for (j = 0; j < CAP_TEST_BURST_SIZE; j++) { |
| 787 | ret = rte_dma_copy(dev_id, vchan, rte_pktmbuf_iova(src), |
| 788 | rte_pktmbuf_iova(dst), COPY_LEN, 0); |
| 789 | if (ret < 0) |
| 790 | ERR_RETURN("Error with rte_dmadev_copy\n"); |
| 791 | |
| 792 | if (rte_dma_burst_capacity(dev_id, vchan) != cap - (j + 1)) |
| 793 | ERR_RETURN("Error, ring capacity did not change as expected\n"); |
| 794 | } |
| 795 | if (rte_dma_submit(dev_id, vchan) < 0) |
| 796 | ERR_RETURN("Error, failed to submit burst\n"); |
| 797 | |
| 798 | if (cap < rte_dma_burst_capacity(dev_id, vchan)) |
| 799 | ERR_RETURN("Error, avail ring capacity has gone up, not down\n"); |
| 800 | } |
| 801 | await_hw(dev_id, vchan); |
| 802 | |
| 803 | for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { |
| 804 | ret = rte_dma_completed(dev_id, vchan, |
| 805 | CAP_TEST_BURST_SIZE, NULL, &dma_err); |
| 806 | if (ret != CAP_TEST_BURST_SIZE || dma_err) { |
| 807 | enum rte_dma_status_code status; |
| 808 | |
| 809 | rte_dma_completed_status(dev_id, vchan, 1, NULL, &status); |
| 810 | ERR_RETURN("Error with rte_dmadev_completed, %u [expected: %u], dma_err = %d, i = %u, iter = %u, status = %u\n", |
| 811 | ret, CAP_TEST_BURST_SIZE, dma_err, i, iter, status); |
| 812 | } |
| 813 | } |
| 814 | cap = rte_dma_burst_capacity(dev_id, vchan); |
| 815 | if (cap != ring_space) |
| 816 | ERR_RETURN("Error, ring capacity has not reset to original value, got %u, expected %u\n", |
| 817 | cap, ring_space); |
| 818 | } |
| 819 |
nothing calls this directly
no test coverage detected